參數(shù)資料
型號(hào)： S5D0127X01-Q0R0
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： MULTISTANDARD VIDEO DECODER/SCALER
中文描述： 多標(biāo)準(zhǔn)視頻解碼器/倍線器
文件頁(yè)數(shù)： 13/96頁(yè)
文件大?。?/td> 1509K
代理商： S5D0127X01-Q0R0
ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 13 OF 96
Modified on May/04/2000
The time constants for the pixel clock tracking loop can be adjusted with the
HFSEL
[1:0]
bits.
In addition to providing the pixel clock, the S5D0127X01 also outputs various timing signals to indicate the
beginning of a line, a field, and for field and frame identification. All the timing and clock pins may be optionally put
into high impedance state. Three-state of these pins are software controlled and initial state of these pins at power
up is controlled via two configuration pins: 3 and 4.
The S5D0127X01 can generate all the video timing without video input. This enables the S5D0127X01 to be used
as a video timing generator for a system that contains both the S5D0127X01 for live video input and a MPEG
decoder which requires a video timing generator.
1.2.3. Horizontal Timing
The S5D0127X01 creates many internal timing signals aligned to the horizontal sync tip (mid-way of the falling
edge of horizontal sync, typically ADC code 36). These include locations of color burst (CBG, CBGW) used in
chrominance processing, back porch (BPG), and sync tip timing signals (SLICE, FS_PULSE) used for AGC and
clamp functions. SLICE is low whenever the input is below half way level of horizontal sync (typically ADC code
36). FS_PULSE is a single clock pulse coincide with the start of SLICE. One of these internal signals can be made
available at the PORTA or PORTB pin at any time.
The chip outputs two horizontal synchronization signals: HS1 and HS2
.
The start and stop locations for these
signals are fully programmable. Offset programmed to
HSxB
,
HSxE
, and
HSxBE0
are added to the default edge
locations as shown in Table 4. Note that there are different modulo numbers for different input video standards and
output pixel rates.
Table 3: Timing for Different Pixel Rates
CCIR 601 Data Rates
Square Pixel Data Rates
Units
M
N,B,G,H,I,D,K,K1,L
M
N,B,G,H,I,D,K,K1,L
Field Rate
60
50
60
50
Hz
Pixels/Line (N)
858
864
780
944
Pixels
Active Pixels/Line
720
720
640
768
Pixels
Active Lines/Frame
480
580
480
580
Lines
Pixel Rate
13.5
13.5
12.27
14.75
MHz
ADC Sampling Rate
27
27
24.54
29.5
MHz
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