
CLOCK CIRCUITS
S3C821A/P821A
7-4
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and
has the following functions:
— Oscillator IRQ wake-up function enable/disable
— Oscillator frequency divide-by value
— System clock signal selection
CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release
(This is called the "IRQ wake-up" function). The IRQ “wake-up” enable bit is CLKCON.7.
After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the
fx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can raise the CPU clock speed to
fx, fx/2, fx/8, or fxt (subsystem clock).
For the S3C821A microcontroller, the CLKCON.2-CLKCON.0 system clock signature code can be any value
(The "101B" setting selects subsystem clock as CPU clock). The reset value for the clock signature code is
"000B".
MSB
LSB
.7
.6
.5
.4
.3
.2
.1
.0
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
D4H, Set 1, R/W
subsystem clock selection bits:
101 B
= select subsystem clock
Other value = select main system clock
Divide-by selection bits for
CPU clock frequency:
00 = fx/16 or fxt
01 = f x/8 or fxt
10 = fx /2 or fxt
11 = fx or fxt (non-divided)
Oscillator IRQ wake-up enable bit:
0 = Enable IRQ for main system
oscillator wake-up function
1 = Disable IRQ for main system
oscillator wake-up function
Main oscillator stop control bits:
00 = No effect
01 = No effect
10 = Stop main oscillator
11 = No effect
NOTE:
Although the value of CLKCON.6-.5 are “10B (value to stop main clock)”,
main clock is not stopped if main system clock (fx) is selected
as CPU clock (fcpu).
(note)
Figure 7-7. System Clock Control Register (CLKCON)