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參數(shù)資料
| 型號： | S3P72P9-QX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, QFP-100 |
| 文件頁數(shù)： | 4/225頁 |
| 文件大?。?/td> | 1303K |
| 代理商： | S3P72P9-QX |
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OSCILLATOR CIRCUITS
S3C72P9/P72P9 (Preliminary Spec)
6-8
SWITCHING THE CPU CLOCK
Together, bit settings in the power control register, PCON, and the system clock mode register, SCMOD,
determine whether a main system or a subsystem clock is selected as the CPU clock, and also how this
frequency is to be divided. This makes it possible to switch dynamically between main and subsystem clocks and
to modify operating frequencies.
SCMOD.3, SCMOD.2, and SCMOD.0 select the main system clock (fx) or a subsystem clock (fxt) and start or
stop main system clock oscillation. PCON.1 and PCON.0 control the frequency divider circuit, and divide the
selected fx clock by 4, 8, or 64,or fxt clock by 4.
NOTE
A clock switch operation does not go into effect immediately when you make the SCMOD and PCON
register modifications — the previously selected clock continues to run for a certain number of machine
cycles.
For example, you are using the default CPU clock (normal operating mode and a main system clock of fx/64)
and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. To do this, you
first need to set SCMOD.0 to "1". This switches the clock from fx to fxt but allows main system clock oscillation
to continue. Before the switch actually goes into effect, a certain number of machine cycles must elapse. After
this time interval, you can then disable main system clock oscillation by setting SCMOD.3 to "1".
This same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first,
clear SCMOD.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles
has elapsed, select the main system clock by clearing all SCMOD values to logic zero.
Following a
RESET, CPU operation starts with the lowest main system clock frequency of 15.3 s at 4.19 MHz
after the standard oscillation stabilization interval of 31.3 ms has elapsed. Table 6-4 details the number of
machine cycles that must elapse before a CPU clock switch modification goes into effect.
Table 6-5. Elapsed Machine Cycles During CPU Clock Switch
AFTER
SCMOD.0 = 0
SCMOD.0 = 1
BEFORE
PCON.1 = 0
PCON.0 = 0
PCON.1 = 1
PCON.0 = 0
PCON.1 = 1
PCON.0 = 1
PCON.1 = 0
N/A
1 MACHINE CYCLE
N/A
PCON.0 = 0
SCMOD.0 = 0
PCON.1 = 1
8 MACHINE CYCLES
N/A
1 MACHINE CYCLES
N/A
PCON.0 = 0
PCON.1 = 1
16 MACHINE CYCLES
1 MACHINE CYCLES
N/A
fx / 4fxt
PCON.0 = 1
SCMOD.0 = 1
N/A
1MACHINE CYCLES
N/A
NOTES:
1.
Even if oscillation is stopped by setting SCMOD.3 during main system clock operation, the stop mode is not entered.
2.
Since the XIN input is connected internally to VSS to avoid current leakage due to the crystal oscillator in stop mode, do
not set SCMOD.3 to "1" or do not use stop instruction when an external clock is used as the main system clock.
3.
When the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur
during the time intervals shown in Table 6-4.
4.
'N/A' means 'not available'.
5.
fx: Main-system clock, fxt: Sub-system clock. When fx is 4.19 MHz, and fxt is 32.768 kHz.
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