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參數(shù)資料
| 型號： | S2204 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad GigaBit Ethernet Transceiver(帶鎖相環(huán)時鐘合成器的四千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | 四個千兆以太網(wǎng)收發(fā)器（帶鎖相環(huán)時鐘合成器的四千兆位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 8/33頁 |
| 文件大小： | 339K |
| 代理商： | S2204 |
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8
QUAD GIGABIT ETHERNET DEVICE
S2204
October 9, 2000 / Revision E
Table 2. Data to 8B/10B Alphabetic Representation
e
B
a
D
]
U
O
D
r
]
N
I
D
0
1
2
3
4
5
6
7
8
9
B
0
1
B
8
n
o
e
s
e
e
R
c
m
u
n
a
h
p
a
b
c
d
e
i
f
g
h
j
Table 3. Operating Rates
E
T
A
R
L
E
S
K
L
C
K
c
L
n
C
e
u
F
E
q
e
R
r
y
F
l
e
t
u
p
t
u
O
S
e
R
O
n
K
e
L
u
C
q
T
e
r
y
c
F
0
0
z
H
M
5
2
1
z
H
M
0
5
2
1
z
H
M
5
2
1
0
1
z
H
M
5
6
z
H
M
0
5
2
1
z
H
M
5
2
1
1
0
z
H
M
5
6
z
H
M
5
2
6
z
H
M
5
6
1
1
z
H
M
5
2
3
z
H
M
5
2
6
z
H
M
5
6
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to insure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 3.
Serial Data Outputs
The S2204 provides LVPECL level serial outputs.
The serial outputs do not require output pulldown
resistors. Outputs are designed to perform optimally
when AC-coupled.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TBC to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. TCLKO will oper-
ate normally regardless of the state of RESET.
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