參數(shù)資料
型號(hào)： S2204
廠商： Applied Micro Circuits Corp.
英文描述： Quad GigaBit Ethernet Transceiver(帶鎖相環(huán)時(shí)鐘合成器的四千兆位以太網(wǎng)收發(fā)器)
中文描述： 四個(gè)千兆以太網(wǎng)收發(fā)器（帶鎖相環(huán)時(shí)鐘合成器的四千兆位以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 7/33頁(yè)
文件大?。?/td> 339K
代理商： S2204
7
S2204
QUAD GIGABIT ETHERNET DEVICE
October 9, 2000 / Revision E
Figure 6. DIN Data Clocking with TBC
Figure 7. DIN Clocking with REFCLK
Table 1. Input Modes
E
D
O
M
T
n
o
r
e
p
O
0
a
d
k
c
o
o
d
e
s
u
K
L
.
n
C
F
n
E
a
h
R
c
.
E
l
D
O
r
M
s
K
O
L
C
F
F
E
R
o
1
o
a
d
k
c
o
o
d
e
s
u
x
n
C
n
a
B
h
T
c
.
E
l
D
O
r
M
s
C
O
B
T
F
.
1. Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
REFCLK
S2204
125 MHz or 62.5 MHz
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
REFCLK
S2204
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
125 MHz
Table 2 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2204. The S2204 will
serialize the parallel data for each channel and will
transmit bit “a” or DIN[0] first.
Frequency Synthesizer (PLL)
The S2204 synthesizes a serial transmit clock from the
reference signal. Upon startup, the S2204 will obtain
phase and frequency lock within 2500 bit times after
the start of receiving reference clock inputs. Reliable
locking of the transmit PLL is assured, but a lock-detect
output in NOT provided.
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