參數(shù)資料
型號: S1D13503F00A
元件分類: 顯示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝: QFP-100
文件頁數(shù): 17/20頁
文件大小: 144K
代理商: S1D13503F00A
6
S1D13503 Series
Address Generator
The Address Generator generates display refresh addresses to be used to access display memory.
MPU / CRT Selector
This block grants access to the display memory from either the MPU or the display refresh circuitry.
Display Data Formatter
The Display Data Formatter reads in the display data from the display memory and outputs the correct format
for all supported gray shade and color selections.
Clock Inputs / Timing
The Timing block generates the internal master clock (MCLK) according to gray-level/color selected and
display memory interface. The master clock (MCLK) can be;
- MCLK = input clock
- MCLK = 1/2 input clock
- MCLK = 1/4 input clock
Pixel clock = input clock (fOSC)
SRAM Interface
This block generates the necessary signals to interface to the Display Memory (SRAM).
相關(guān)PDF資料
PDF描述
S1DGPC SLIDE SWITCH, SPDT, LATCHED, 0.05A, 48VDC, THROUGH HOLE-STRAIGHT
S1F 1.2 A, 50 V, SCR, TO-92
S2A 1.5 A, 100 V, SCR, TO-92
S2D 1.5 A, 400 V, SCR, TO-92
S2M 1.5 A, 600 V, SCR, TO-92
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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