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參數(shù)資料
| 型號： | S1D13503F00A |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 144K |
| 代理商： | S1D13503F00A |
13
S1D13503 Series
x Summary of Configuration Options
The S1D13503 requires some configuration information on power-up. This information is provided through
the SRAM data lines VD[0...15]. The state of these pins are read on the falling edge of RESET and used to
configure the following options:
Summary of Power On / Reset Options
Note : The S1D13503 has internal pull down resistors on these pins and therefore will be pulled down and read
on a logic “0” after RESET. If pull up resistors are required refer to Table “Input Specifications” on page
16 for pull down resistor values.
Example: If an ISA bus (no byte swap) with memory segment “A” and I/O location 300h are used, the
corresponding settings of VD15-VD0 would be:
I/O and Memory Addressing Example
Where x = don't care; 1 = connected to pull-up resistor; 0 = no pull-up resistor
Pin Name
Value on this pin at falling edge of RESET is used to congure:
(1/0)
1
0
VD0
16-bit host bus interface
8-bit host bus interface
VD1
Use direct-mapping for I/O accesses
Use internal index register for I/O accesses
VD2
MC68000 MPU interface
MPU / Bus interface with memory accesses
controlled by a READY (WAIT#) signal
VD3
Swap of high and low data bytes in 16-bit bus
inter-face
No byte swap of high and low data bytes in 16-bit
bus interface
VD12–VD4
Select I/O mapping address bits [9:1].
VD15–VD13
Select memory mapping address bits [3:1]
These nine bits are latched on power-up and are compared to the MPU address bits [9–1]. A valid
I/O cycle combined with a valid address will enable the internal I/O decoder. Therefore, both types
of I/O mapping are limited to even address boundaries to determine either the absolute or indexed
I/O address of the first register. Note that a “valid I/O cycle” includes IOCS# being toggled low.
These three bits are latched on power-up and are compared to the MPU address bits [19–17].
A valid memory cycle combined with a valid address will enable the internal memory decoder. As
only the three most significant bits of the address are compared, the maximum amount of memory
supported is 128K bytes. Note that a “valid memory cycle” includes MEMCS# being toggled low.
When using 128K-byte memory it must be mapped at an even address such that all 128K bytes is
available without a change in state on A17, as this would invalidate the internal compare logic.
Pin Name
8-Bit ISA Bus
16-Bit ISA Bus
Index Register
Direct Mapping
Index Register
Direct Mapping
VD0
0
VD1
0
1
0
1
VD2
0
VD3
0
01
1
0
VD12–VD4
11 0000 000
11 0000 xxx
11 0000 000
11 0000 xxx
VD15–VD13
101
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1DGPC | SLIDE SWITCH, SPDT, LATCHED, 0.05A, 48VDC, THROUGH HOLE-STRAIGHT |
| S1F | 1.2 A, 50 V, SCR, TO-92 |
| S2A | 1.5 A, 100 V, SCR, TO-92 |
| S2D | 1.5 A, 400 V, SCR, TO-92 |
| S2M | 1.5 A, 600 V, SCR, TO-92 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1D13503F00A1 | 制造商:Epson Electronics America Inc 功能描述: |
| S1D13503F00A100 | 制造商:Epson Electronics America Inc 功能描述:LCD DRVR 3V/3.3V/5V 80-Pin TQFP |
| S1D13503F00A200 | 功能描述:LCD 驅(qū)動器 LCD CONTROLLER RoHS:否 制造商:Maxim Integrated 數(shù)位數(shù)量:4.5 片段數(shù)量:30 最大時鐘頻率:19 KHz 工作電源電壓:3 V to 3.6 V 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:PDIP-40 封裝:Tube |
| S1D13503F01A | 制造商:EPSON 制造商全稱:EPSON 功能描述:LCD Controller ICs |
| S1D13503F01A200 | 功能描述:LCD 驅(qū)動器 LCD CONTROLLER RoHS:否 制造商:Maxim Integrated 數(shù)位數(shù)量:4.5 片段數(shù)量:30 最大時鐘頻率:19 KHz 工作電源電壓:3 V to 3.6 V 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:PDIP-40 封裝:Tube |
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