參數(shù)資料
型號(hào): S1D13503F00A
元件分類(lèi): 顯示控制器
英文描述: 1024 X 768 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝: QFP-100
文件頁(yè)數(shù): 3/20頁(yè)
文件大?。?/td> 144K
代理商: S1D13503F00A
11
S1D13503 Series
s PIN DESCRIPTION
x Description
Key:
I
= Input
O
= Output
I/O
= Bidirectional (Input/Output)
P
= Power pin
COx
= CMOS level output driver, x denotes driver type (see Table “Output Specifications” on page
15)
COxS
= CMOS level output driver with slew rate control for noise reduction, x denotes driver type
(see Table “Output Specifications” on page 15)
TSx
= Tri-state CMOS level output driver, x denotes driver type (see Table “Output Specifications”
on page 15)
TSxD2
= Tri-state CMOS level output driver with pull down resistor (typical values of 100 k
/200 k at
5 V/3.0 V respectively), x denotes driver type (see Table “Output Specifications” on page 15)
TTL
= TTL level input
TTLS
= TTL level input with hysteresis
Bus Interface
Pin Name
Type
F00A
Pin No .
F01A
Pin No .
D00A
Pad No .
Driver
Descr iption
DB0–DB15
I/O
94–100,
1, 4 –11
91–98,
1–8
118–119,
121–125,
128, 4–11
TS2
These pins are connected to the system data bus. In 8-bit bus
mode, DB8–DB15 must be tied to VDD.
AB0
12
13
TTLS
In MC68000 MPU interface, this pin is connected to the Upper
Data Strobe (UDS#) pin of MC68000. In other MPU/Bus inter-
faces, this pin is connected to the system address bus.
AB1–AB19
I
13–31
10–28
14–20,
22–30,
32–33, 36
TTL
BHE#
I
91
88
9
113
TTLS
In MC68000 MPU interface, this pin is connected to the Lower
Data Strobe (LDS#) pin of MC68000. In other MPU/Bus inter-
faces, this pin is the Byte High Enable input for use with 16-bit
system. In 8-bit bus mode tie the BHE# input to VDD.
IOCS#
I
84
81
103
TTLS
Active low input to select one of sixteen internal registers.
IOW#
I
85
82
104
TTLS
In MC68000 MPU interface, this pin is connected to the R/W#
pin of MC68000. This input pin defines whether the data trans-
fer is a read (active high) or write (active low) cycle. In other
MPU/Bus interfaces, this is the active low input to write data
into an internal register.
IOR#
I
86
83
106
TTLS
In MC68000 MPU interface, this pin is connected to the AS#
pin of MC68000. This input pin indicates a valid address is
available on the address bus. In other MPU/Bus interfaces, this
is the active low input to read data from an internal register.
MEMCS#
I
87
84
107
TTLS
Active low input to indicate a memory cycle.
MEMW#
I
88
85
109
TTLS
Active low input to indicate a memory write cycle. This pin
should be tied to VDD in an MC68000 MPU interface.
MEMR #
89
86
110
TTLS
Active low input to indicate a memory read cycle. This pin
should be tied to VDD in an MC68000 MPU interface.
READY
O
90
87
112
TS3
For MC68000 MPU interface, this pin is connected to the
DTACK# pin of MC68000 and is driven low when the data
transfer is complete. In other MPU/Bus interfaces, this output
is driven low to force the system to insert wait states when
needed.
READY is placed in a high impedance (Hi-Z) state after the
transfer is completed.
RESET
I
32
29
37
TTLS
Active high input to force all signals to their inactive states.
These pins are connected to the system address bus.
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