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參數(shù)資料
| 型號(hào)： | S1D13305F00A |
| 元件分類(lèi)： | 顯示控制器 |
| 英文描述： | 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60 |
| 封裝： | QFP5-60 |
| 文件頁(yè)數(shù)： | 66/94頁(yè) |
| 文件大?。?/td> | 541K |
| 代理商： | S1D13305F00A |
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S1D13305 Series
EPSON
63
Technical Manual
12.2. Supply Current during Display Memory Access
The 24 address and data lines of the S1D13305 series
cycle at one-third of the oscillator frequency, fOSC. The
charge and discharge current on these pins, IVOP, is given
by the equation below. When IVOP exceeds IOPR, it can be
estimated by:
IVOP
∝ C V f
where C is the capacitance of the display memory bus, V
is the operating voltage, and f is the operating frequency.
If VOPR = 5.0V, f = 1.0 MHz, and the display memory bus
capacitance is 1.0 pF per line:
IVOP
≤ 120 A / MHz × pF
To reduce current flow during display memory accesses,
it is important to use low-power memory, and to mini-
mize both the number of devices and the parasitic capaci-
tance.
13. OSCILLATOR CIRCUIT
The S1D13305 series incorporates an oscillator circuit. A
stable oscillator can be constructed simply by connecting
an AT-cut crystal and two capacitors to XG and XD, as
shown in the figure below. If the oscillator frequency is
increased, CD and CG should be decreased proportion-
ally.
Note that the circuit board lines to XG and XD must be as
short as possible to prevent wiring capacitance from
changing the oscillator frequency or increasing the power
consumption.
Figure 52. Crystal oscillator
S1D13305 series
XD
XG
CD
CG
CD = 3 to 20 pF
CG = 2 to 18 pF
Load impedance = 700
(max)
14. STATUS FLAG
The S1D13305 series has a single bit status flag.
D6: X line standby
Figure 53. Status flag
The D6 status flag is HIGH for the TC/R-C/R cycles at the
end of each line where the S1D13305 series is not reading
the display memory. The microprocessor may use this
period to update display memory without affecting the
display, however it is recommended that the display be
turned off when refreshing the whole display.
D7
D0
X
D6
XXXXXXX: Don’t care
Figure 54. C/R to TC/R time difference
tm
tTC/R
LP
XSCL
tC/R
CS
A0
RD
D6 (flag)
0
0: Period of retrace lines
1: Period of display
DISPLAY MEMORY INTERFACE/OSCILLATOR CIRCUIT/STATUS FLAG
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1D13305F00A100 | 制造商:SEIKO 功能描述: |
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| S1D13305F00B100 | 制造商:Epson Electronics America Inc 功能描述:LCD DRVR 3V/3.3V/5V 80-Pin TQFP |
| S1D13501F00A100 | 制造商:Epson Electronics America Inc 功能描述:LCD DRVR 3V/3.3V/5V 80-Pin TQFP |
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