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參數(shù)資料
| 型號： | S1D13305F00A |
| 元件分類： | 顯示控制器 |
| 英文描述： | 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60 |
| 封裝： | QFP5-60 |
| 文件頁數(shù)： | 62/94頁 |
| 文件大小： | 541K |
| 代理商： | S1D13305F00A |
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S1D13305 Series
EPSON
59
Technical Manual
11. MICROPROCESSOR INTERFACE
11.1. System Bus Interface
SEL1, SEL2, A0, RD, WR and CS are used as control
signals for the microprocessor data bus. A0 is normally
connected to the lowest bit of the system address bus.
SEL1 and SEL2 change the operation of the RD and WR
pins to enable interfacing to either an 8080 or 6800 family
bus, and should have a pull-up or pull-down resistor.
With microprocessors using an 8080 family interface, the
S1D13305 series is normally mapped into the I/O address
space.
11.1.1. 8080 series
Table 24. 8080 series interface signals
11.1.2. 6800 series
Table 25. 6800 series interface signals
11.2. Microprocessor Synchronization
The S1D13305 series interface operates at full bus speed,
completing the execution of each command within the
cycle time,
tCYC . The controlling microprocessor’s per-
formance is thus not hampered by polling or handshaking
when accessing the S1D13305 series.
Display flicker may occur if there is more than one
consecutive access that cannot be ignored within a frame.
The microprocessor can minimize this either by perform-
ing these accesses intermittently, or by continuously
checking the status flag (D6) and waiting for it to become
HIGH.
11.2.1. Display status indication output
When CS, A0 and RD are LOW, D6 functions as the
display status indication output. It is HIGH during the
TV-mode vertical retrace period or the LCD-mode hori-
zontal retrace period, and LOW, during the period the
controller is writing to the display. By monitoring D6 and
writing to the data memory only during retrace periods,
the display can be updated without causing screen flicker.
11.2.2. Internal register access
The SYSTEM SET and SLEEP IN commands can be
used to perform input/output to the S1D13305 series
independently of the system clock frequency. These are
the only commands that can be used while the S1D13305
series is in sleep mode.
11.2.3. Display memory access
The S1D13305 series supports a form of pipelined pro-
cessing, in which the microprocessor synchronizes its
processing to the S1D13305 series timing. When writing,
the microprocessor first issues the MWRITE command.
It then repeatedly writes display data to the S1D13305
series using the system bus timing. This ensures that the
microprocessor is not slowed down even if the display
memory access times are slower than the system bus
access times. See Figure 47.
When reading, the microprocessor first issues the MREAD
command, which causes the S1D13305 series to load the
first read data into its output buffer. The microprocessor
then reads data from the S1D13305 series using the
system bus timing. With each read, the S1D13305 series
reads the next data item from the display memory ready
for the next read access. See Figure 48.
A0 RD WR
Function
0
1
Status flag read
101
Display data and cursor address
read
0
1
0
Display data and parameter write
1
0
Command write
0
1
Status flag read
111
Display data and cursor address
read
0
1
Display data and parameter write
1
0
1
Command write
Function
E
R/W
A0
MICROPROCESSOR INTERFACE
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