參數(shù)資料
型號: S1D13305F00A
元件分類: 顯示控制器
英文描述: 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60
封裝: QFP5-60
文件頁數(shù): 47/94頁
文件大小: 541K
代理商: S1D13305F00A
S1D13305 Series
EPSON
45
Technical Manual
9.2.3. Display scan timing
Figure 32 shows the basic timing of the S1D13305 series.
One display memory read cycle takes nine periods of the
system clock,
φ0 (fOSC ). This cycle repeats (C/R + 1)
times per display line.
When reading, the display memory pauses at the end of
each line for (TC/R - C/R) display memory read cycles,
though the LCD drive signals are still generated. TC/R
may be set to any value within the constraints imposed by
C/R,
fOSC , fFR , and the size of the LCD panel, and it may
be used to fine tune the frame frequency. The micropro-
cessor may also use this pause to access the display
memory data.
Figure 32. Display memory basic read cycle
T0
T1
T2
Display read cycle interval
Graphics read interval
Character read interval
Character generator
read interval
φ0
VCE
VA
Figure 33. Relationship between TC/R and C/R
Frame
period
Display period
Divider frequency
period
TC/R
C/R
O
O
R
Line 1
2
3
(L/F)
LP
Note: The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active
only at the end of the lower screen’s display interval.
DISPLAY CONTROL FUNCTIONS
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