參數(shù)資料
型號: S1D13305F00A
元件分類: 顯示控制器
英文描述: 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60
封裝: QFP5-60
文件頁數(shù): 13/94頁
文件大?。?/td> 541K
代理商: S1D13305F00A
14
EPSON
S1D13305 Series
Technical Manual
Signal
Symbol
Parameter
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Unit
Condition
Min.
Max.
Min.
Max.
EXT
φ0tC
Clock period
100
125
ns
tW
VCE HIGH-level
pulsewidth
tC – 50
tC – 50
ns
VCE
tCE
VCE LOW-level
pulsewidth
2tC – 30
2tC – 30
ns
tCYW
Write cycle time
3tC
—3tC
—ns
tAHC
Address hold time from
2tC – 30
2tC – 40
ns
falling edge of VCE
tASC
Address setup time to
tC – 70
tC – 110
ns
falling edge of VCE
VA0 to
tCA
Address hold time from
0—
ns
VA15
rising edge of VCE
tAS
Address setup time to
0—
ns
falling edge of VWR
tAH2
Address hold time from
10
10
ns
rising edge of VWR
tWSC
Write setup time to
tC – 80
tC – 115
ns
VWR
falling edge of VCE
tWHC
Write hold time from
2tC – 20
2tC – 20
ns
falling edge of VCE
tDSC
Data input setup time to
tC – 85
tC – 125
ns
falling edge of VCE
VD0 to
tDHC
Data input hold time
2tC – 30
2tC – 30
ns
VD7
from falling edge of VCE
tDH2
Data hold time from
550
5
50
ns
rising edge of VWR
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.
Ta = –20 to 75
°C
CL = 100
pF
SPECIFICATIONS
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