參數(shù)資料
型號： S1C63567F0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁數(shù)： 44/172頁
文件大?。?/td> 1349K
代理商： S1C63567F0A0100
128
EPSON
S1C63567 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Telephone Function)
PAUSE: Pause function (FF14HD1)
Executes the pause function.
When "1" is written: Execute pause function
When "0" is written: Cancel pause function
Reading: Always "0"
Writing "1" to PAUSE executes the pause function. The pause time set by the PTS register is inserted to
the DP output signal. An interrupt occurs when the pause is released and the PAUSE bit is automatically
cleared to "0".
This bit is write-only, and so is always "0" at reading.
FLASH: Flash function (FF14HD0)
Executes the flash function.
When "1" is written: Execute flash function
When "0" is written: Cancel flash function
Reading: Always "0"
Writing "1" to FLASH executes the flash function. The DP, XRMUTE (R11) and XTMUTE (R10) terminals
go Low (VSS) level during the flash period set by the FTS register and then an interrupt occurs. At the
same time the FLASH bit is automatically cleared to "0" by the interrupt.
This bit is write-only, and so is always "0" at reading.
HF: Handfree (FF14HD3)
Controls the handfree function and HFO signal output.
When "1" is written: ON (High level output on R13 terminal)
When "0" is written: OFF (Low level output on R13 terminal)
Reading: Valid
This register controls the HFO signal output to the R13 terminal when the HFO function has been se-
lected. The HFO output function is set by writing "1" to the CHFO register (FF13HD3). In this case, the
R13 register must be fixed at "1" and the R13HIZ register at "0".
When "1" is written to the HF register, the HFO (R13) terminal goes High (VDD) level.
When "0" is written, the HFO (R13) terminal goes Low (VSS) level.
At initial reset, this register is set to "0".
IDP0–IDP3: Inter-digit pause time selection (FF15H)
Select an inter-digit pause time for the pulse mode from among the 15 types shown in Table 4.14.10.4.
Table 4.14.10.4 Selection of inter-digit pause times
D3
0
D2
0
1
D1
0
1
0
1
D0
0
1
0
1
0
1
0
1
IDP
Inter-digit pause
time (msec)
Unavailable *
94
188
281
375
469
563
656
D3
1
D2
0
1
D1
0
1
0
1
D0
0
1
0
1
0
1
0
1
IDP
Inter-digit pause
time (msec)
750
844
938
1031
1125
1219
1313
1406
Do not write "0" (0000B) to the IDP register because it may cause a malfunction.
The specified inter-digit pause time will be inserted after each dialing pulse digit. This selection is valid
only for pulse mode.
At initial reset, this register is set to "1000B" (750 msec).
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