
I-116
EPSON
S1C62440/624A0/624C0/62480 TECHNICAL HARDWARE
CHAPTER 11: SERIAL INTERFACE
Data Input/Output and Interrupt Function
The serial interface of S1C62440/4A0/4C0/480 can input/
output data via the internal 8 bits shift register. The shift
register operates by synchronizing with either the synchro-
nous clock output from SCLK terminal (master mode), or the
synchronous clock input to SCLK (slave mode).
The serial interface generates interrupt on completion of the
8 bits serial data input/output. Detection of serial data
input/output is done by the counting of the synchronous
clock (SCLK); the clock completes input/output operation
when 8 counts (equivalent to 8 cycles) have been made and
then generates interrupt.
The serial data input/output procedure data is explained
below:
(1) Serial data output procedure
The S1C62440/4A0/4C0/480 serial interface is capable
of outputting parallel data as serial data, in units of 8
bits.
By setting the parallel data to data registers SD0–SD3
and SD4–SD7 individually and writing "1" to SCTRG
(F7AH[D3]), it synchronizes with the synchronous clock
and serial data is output at the SOUT terminal. The
synchronous clock used here is as follows: in the master
mode, internal clock which is output to the SCLK termi-
nal while in the slave mode, external clock which is input
from the SCLK terminal. The serial output of the SOUT
terminal changes with the falling edge of the clock that is
input or output from the SCLK terminal.
When the output of the 8 bits data from SD0 to SD7 is
completed, the interrupt factor flag ISIO is set to "1" and
interrupt is generated. Moreover, the interrupt can be
masked by the interrupt mask register EISIO. Note,
however, that regardless of the setting of the interrupt
mask register, the interrupt factor flag is set to "1" after
output of the 8 bits data.
11.4