
II-16
EPSON
S1C62440/624A0/624C0/62480 TECHNICAL SOFTWARE
CHAPTER 4: DATA MEMORY
Table 4.2.1(c) I/O data memory map (F50H–F54H, F60H–F63H)
*
1 Initial value following initial reset
*
2 Undefined
*
3 When selecting options enclosed in brackets [ ] as output option, the output register
will function as register only and will not affect the individual outputs
*
4 In the S1C62440, it can be used only as a port for output
*
5 In the S1C62440, it can be used only as a port for I/O port
*
6 In the S1C62440, the F50H, F51H and F63H cannot be used
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
F50H
R00
R/W
R03
R02
R01
R00
X
Output port (R03) / External memory address (A3)
Output port (R02) / External memory address (A2)
Output port (R01) / External memory address (A1)
Output port (R00) / External memory address (A0)
High
Low
R01
R02
R03
F51H
R10
R/W
R13
R12
R11
R10
X
Output port (R13) / External memory address (A7)
Output port (R12) / External memory address (A6)
Output port (R11) / External memory address (A5)
Output port (R10) / External memory address (A4)
High
Low
R11
R12
R13
*2
*6
F60H
P00
R/W
P03
P02
P01
P00
X
I/O port (P03) / External memory data (D3)
I/O port (P02) / External memory data (D2)
I/O port (P01) / External memory data (D1)
I/O port (P00) / External memory data (D0)
High
Low
P01
P02
P03
*5
F61H
P10
R/W
P13
P12
P11
P10
X
I/O port (P13) / External memory data (D7)
I/O port (P12) / External memory data (D6)
I/O port (P11) / External memory data (D5)
I/O port (P10) / External memory data (D4)
High
Low
P11
P12
P13
*2
*6
F62H
P20
R/W
W
P23
P22
P21
P20
X
I/O port (P23) / External memory CS (CS3)
I/O port (P22) / External memory CS (CS2)
I/O port (P21) / External memory CS (CS1)
I/O port (P20) / External memory CS (CS0)
High
Low
P21
P22
*2
F63H
P30
R/W
P33
P32
P31
P30
X
I/O port / Dedicated output port (P33)
I/O port / Dedicated output port (P32)
I/O port / Dedicated output port (P31)
I/O port / Dedicated output port (P30)
High
Low
P31
P32
P33
*2
P23
*5
F52H
R20
R/W
R23
R22
R21
R20
X
Output port (R23) / External memory address (A11)
Output port (R22) / External memory address (A10)
Output port (R21) / External memory address (A9)
Output port (R20) / External memory address (A8)
High
Low
R21
R22
R23
*4
F53H
R30
R/W
X
Output port (R33)
PTCLK output
[SRDY (SIO READY)]
Output port (R32)
[External memory read (RD)]
[External memory write (WR)]
High
Off
High
Low
On
Low
R31
R32
R33
*2
F54H
R40
R/W
R43
R42
R41
R40
1
Output port (R43)
Buzzer output (BZ)
Output port (R42)
Clock output (FOUT)
[Buzzer inverted output (BZ)]
Output port (R41)
LCD frame signal (FR)
Output port (R40)
Clock inverted output (FOUT)
LCD synchronous signal (CL)
High
Off
High
Off
High
Off
High
Off
Low
On
Low
On
Low
On
Low
On
R41
R42
R43
*3
R33
R32
R31
R30
Output port (R31) / External memory address (A13)
Output port (R30) / External memory address (A12)
*4