
I-10
EPSON
S1C62440/624A0/624C0/62480 TECHNICAL HARDWARE
CHAPTER 1: INTRODUCTION
1.4 Pin Description
Table 1.4.1 Pin description
V
–V
CA–CF
OSC1
OSC2
OSC3
OSC4
COM0–15
SEG0–39
SEG40–50
RESET
TEST
V
K00–K03
K10–K13
P00–P03
P10–P13
P20–P23
P30–P33
R00–R03
R10–R13
R20–R23
R30–R33
R40–R43
SIN
SOUT
SCLK
DD
SS
S1
L1
REF
125
117
122
127, 128
1–3
10–6, 4
124
123
121
120
11–26
67–35
33–27
–
118
119
126
79–76
75–72
95–92
91–88
87–84
83–80
116–113
112–109
108–105
104–101
100, 99, 97, 96
71
70
68
S1C62440
Pin Name
I
–
I
O
I
O
I
O
I
I/O
O
I
O
I/O
In/Out
Power (+)
Power (-)
Internal logic system/oscillation system regulated voltage
Function
LCD common output
(1/8 duty or 1/16 duty is selected on software)
LCD segment output
Initial reset input terminal
Testing input terminal
LCD system power test terminal
Input ports
(Use of pull up resistor is selected with mask option)
Input/Output ports
(Complementary output or Nch open drain output,
and DC output or external data bus output are selected
with mask option)
LCD system power
LCD system voltage booster condenser
connecting terminal
134
125
130
136–140
2, 1
144–141
132
131
129
128
4–18
20
74–51
49–37
34–32
31–21
126
127
135
87–85, 83
82–79
104–101
100–98, 96
95–92
91–88
124–121
120–117
116–113
112–109
108–105
78
77
76
S1C624C0/480
S1C624A0
119
109
115
121–125
5, 4, 2
128–126
117
116
113
112
7–22
67, 65–40
38, 36
34–24
–
110
111
120
80–77
76–73
92–89
88–85
84–81
–
108–105
104–101
97, 96, 94, 93
72
71
70
Pin No
Output ports
(Complementary output or Nch open drain output,
and DC output or external address bus output,
buzzer output, FOUT output, SRDY output, CL output,
and FR output are selected by mask option)
Serial interface data input terminal
Serial interface data output terminal
Serial interface clock input/output terminal
L5
1/4 bias generated internally
1/5 bias generated externally
(selected by mask option)
Crystal or CR (selected by mask option only for
S1C62440/4C0/480) oscillator input terminal
Crystal or CR (selected by mask option only for
S1C62440/4C0/480)
oscillator output terminal (CD built-in)
CR or ceramic oscillator input terminal
(selected by mask option)
CR or ceramic oscillator output terminal
(selected by mask option)
*
The TEST (test terminal) is used when the IC load is being detected.
During ordinary operation be certain to connect this pin to VDD.
*
Leave the VREF terminal unconnected (N.C.).