
7 Oscillator Circuit (OSC)
7-6
Seiko Epson Corporation
S1C17601 TECHNICAL MANUAL
7.5 Clock Switching
The system clock select section of the S1C17601 consists of dual stages, high-speed clock (HSCLK) select and
OSC1-HSCLK select. Figure 7.5.1 shows the configuration of the system clock select section.
HSCLKSEL
HSCLK
IOSC
OSC3
OSC1
CLKSRC
System clock
Figure 7.5.1: System clock select section
High-speed Clock (HSCLK) Selection
The S1C17601 includes the IOSC and OSC3 oscillator circuits to generate high-speed clocks (HSCLK). The IOSC
oscillator circuit is turned on, and the IOSC clock is selected for HSCLK when operation starts after the initial reset.
To select OSC3 for HSCLK, turn on the OSC3 oscillator circuit (see section 7.3), and then write 1 to HSCLK
(D1/OSC_SRC register). To select IOSC for HSCLK, turn on the IOSC oscillator circuit (see section 7.2), and then
write 0 to HSCLK.
It takes one HSCLK cycle at minimum or one OSC1 cycle at maximum to switch clocks from OSC1 to HSCLK
and vice versa.
HSCLKSEL: High-speed Clock Select Bit in the Clock Source Select (OSC_SRC) Register (D1/0x5060)
Note: To select HSCLK, both of the IOSC and OSC3 must be turned on. Writing to HSCLKSEL while both
of them are not turned on does not switch HSCLK, and does not change the HSCLKSEL value.
OSC1 HSCLK selection
The S1C17601 includes the OSC1 oscillator circuit to generate low-speed clocks. Either of the OSC1 or HSCLK
can be selected for the system clock. HSCLK is selected when operation starts after the initial reset.
To select OSC1 for the system clock, turn on the OSC1 oscillator circuit (see section 7.4), and then write 1 to
CLKSRC (D1/OSC_SRC register). To select HSCLK for the system clock, write 0 to SRCSRC while HSCLK is
operating.
It takes one HSCLK cycle at minimum or one OSC1 cycle at maximum to switch clocks from OSC1 to HSCLK
and vice versa.
CLKSRC: System Clock Source Select Bit in the Clock Source Select (OSC_SRC) Register (D0/0x5060)
Oscillator circuits other than selected for the system clock and are not used as the operating clock for peripheral
circuits can be stopped to reduce current consumption.
Notes: To select OSC1_HSCLK, both of the OSC1 and HSCLK must be operating. Writing to
HSCLKSEL while one of them is not operating does not switch the system clock, and does
not change the CLKSRC value.
The table 7.5.1 shows combinations of register settings permitted to select OSC1-HSCLK.
Table 7.5.1: Combinations of settings permitted to select OSC1-HSCLK
IOSC
OSC3
OSC1
HSCLKSEL
On
On
Off
On
0
Off
On
1
The oscillator circuit selected for the system clock cannot be turned off.
Sequential access of write/read to the CLKSRC register is prohibited. Between write and
read access instructions to CLKSRC, insert at least one instruction unrelated to access to
the CLKSRC register.