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參數(shù)資料
| 型號(hào)： | S1C17601F00E100 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8.2 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, TQFP-64 |
| 文件頁(yè)數(shù)： | 217/468頁(yè) |
| 文件大小： | 3387K |
| 代理商： | S1C17601F00E100 |
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21 I2C Slave (I2CS)
21-8
Seiko Epson Corporation
S1C17601 TECHNICAL MANUAL
The ACK bit indicates that the master could receive data. It is also a transmit request bit, therefore, the next
transmit data must be written in advance. Receiving ACK generates a clock stretch status when the clock stretch
function has been enabled, so data can be written after an ACK is received.
An NAK will be returned from the master if the master could not receive data or when the master terminates
data reception. In this case a clock stretch status is not generated even if the clock stretch function has been
enabled.
Read DA_NAK (D1/I2CS_STAT register) to check if an ACK is returned or if a NAK is returned. DA_NAK
is set to 0 when an ACK is returned or set to 1 when a NAK is returned. An interrupt can be generated when
DA_NAK is set to 1, so an error or termination handling can be performed in the interrupt handler routine.
DA_NAK is cleared by writing 1.
DA_NAK: NAK Receive Status Bit in the I2C Slave Status (I2CS_STAT) Register (D1/0x4368)
The SDA1 line status during data transmission is input in the module and is compare with the output data. The
comparison results are set to DMS (D3/I2CS_STAT register). DMS is set to 0 when data is output correctly. If
the SDA1 line status is different from the output data, DMS is set to 1. This may be caused by a low pull-up
resistor value or another device that is controlling the SDA1 line. An interrupt can be generated when DMS is
set to 1, so an error handling can be performed in the interrupt handler routine. DMS is cleared by writing 1.
DMS: Output Data Mismatch Bit in the I2C Slave Status (I2CS_STAT) Register (D3/0x4368)
Data reception
The following describes a data receive procedure.
The I2C slave module starts data receive process when SELECTED is set to 1 and R/W is set to 0. The receive
data bits are input from the SDA1 pin in sync with the SCL1 input clock sent from the master. When the
8-bit data (MSB first) is received in the shift register, the received data is loaded to RDATA[7:0] (D[7:0]/
I2CS_RECV register).
RDATA[7:0]: I2C Slave Receive Data Bits in the I2C Slave Receive Data (I2CS_RECV) Register (D[7:0]/0x4362)
When the received data is loaded to RDATA[7:0], RXRDY (D4/I2CS_ASTAT register) is set to 1 to issue a
request to the application program to read RDATA[7:0]. An interrupt can be generated when RXRDY is set to 1,
so the received data should be read in the interrupt handler routine. RXRDY is cleared by writing 1.
RXRDY: Receive Data Ready Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D4/0x436a)
When the clock stretch function is disabled (default)
When the clock stretch function has been disabled, data must be read from the I2CS_RECV register within
7 cycles of the I2C slave clock (SCL1) from RXRDY being set to 1.
When the clock stretch function is enabled
When the clock stretch function has been enabled, the I2C slave module pulls down the SCL1 pin to low to
generate a clock stretch (wait) status until the received data is read from the I2CS_RECV register.
If the next data has been received without reading the received data, RDATA[7:0] will be overwritten. In this
case, RXOVF (D5/I2CS_STAT register) is set to 1 to indicate that the received data has been overwritten. An
interrupt can be generated when RXOVF is set to 1, so an error handling should be performed in the interrupt
handler routine. RXOVF is cleared by writing 1.
RXOVF: Receive Data Overflow Bit in the I2C Slave Status (I2CS_STAT) Register (D5/0x4368)
To return NAK during data reception
During data reception (master transmission), the I2C slave module sends back an ACK (SDA1 = low) every
time an 8-bit data has been received (by default setting). The response code can be changed to NAK (SDA1 =
Hi-Z) by setting NAK_ANS (D5/I2CS_CTL register). ACK will be sent when NAK_ANS is 0 or NAK will be
sent when NAK_ANS is set to 1.
NAK_ANS: NAK Answer Bit in the I2C Slave Control (I2CS_CTL) Register (D5/0x4366)
NAK_ANS should be set within 7 cycles of the I2C slave clock (SCL1) after RXRDY has been set to 1 by
receiving data just prior to one required for returning NAK.
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| S1C17602 | 制造商:EPSON 制造商全稱(chēng):EPSON 功能描述:16-bit Single Chip Microcontroller |
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