- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384892 > RTL8019AS (Electronic Theatre Controls, Inc.) Realtek Full-Duplex Ethernet Controller with Plug and Play Function (RealPNP) PDF資料下載
參數(shù)資料
| 型號： | RTL8019AS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Realtek Full-Duplex Ethernet Controller with Plug and Play Function (RealPNP) |
| 中文描述： | 瑞昱全雙工以太網(wǎng)控制器即插即用功能（RealPNP） |
| 文件頁數(shù)： | 43/50頁 |
| 文件大?。?/td> | 992K |
| 代理商： | RTL8019AS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
8019AS.doc
2001-05-10
·R￥bééa￥÷|3--¤￥q
SPECIFICATION
RTL8019AS
43
Mode 3:
Loopback through the cable (LB1=1, LB0=1 in TCR)
The packets are transmitted via the MAU onto the network and RTL8009 receives all
incoming packets (not only the MAU-loopbacked Tx data) in the meantime.
SNI
83910
NIC
8390
MAU
8392/RTL8005
CABLE
Ref:
q
Alignment of the Reception FIFO
The reception FIFO is an 8-byte ring structure. The first received byte is put at location zero.
When the location pointer goes to the end of the FIFO, it wraps to the beginning of the FIFO and
overwrites the previous data. At the end of the packet reception, the FIFO contents are in the
"order" (from the ring structure's view) as shown below.
(1) CRC enabled (CRC bit in TCR=0)
s
1-byte received packet data
s
4-byte CRC
s
1-byte lower byte count
s
1-byte upper byte count
s
1-byte upper byte count
(2) CRC disabled (CRC bit in TCR=1)
s
5-byte received packet data
s
1-byte lower byte count
s
1-byte upper byte count
s
1-byte upper byte count
6.6.2. To Implement Loopback Test
(1) To verify the integrity of data path
s
set RCR=00h to accept physical packet
s
set PAR0-5 to accept packet
s
set DCR=40h (8-bit slot) or 43h (16-bit slot)
s
set TCR=02h, 04h, 06h to do loopback test 1, 2, 3 respectively
s
set CRC enabled (CRC=0 in TCR)
s
clear ISR
s
tx a packet and check ISR
s
check FIFO after loopback
Note: Loopback mode 3 is sensitive to the network traffic, so the values of FIFO may be not
correct.
(2) To verify CRC logic
q
Select a loopback mode (e.g. mode 2) to test
A. To test CRC generator
s
set RCR=00h to accept physical packet
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RTL8168 | INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS TM |
| RUE250U | Poly Switch PTC DEVICES |
| RV5C338A | 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
| RV5C338A-E2 | DIODE ZENER SINGLE 200mW 8.2Vz 20mA-Izt 0.02549 0.1uA-Ir 6.5 SOD-323 3K/REEL |
| RV5C386A | I2C-bus Real-Time Clock ICs with Voltage Monitoring Function |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RTL8019AS-LF | 制造商:Realtek Semiconductor 功能描述:RTL8019 Series 16 kB Sram ISA Full Duplex Ethernet Controller - PQFP-100 |
| RTL8021N(V1.2) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| RTL8021N-GR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| RTL8029AS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Realtek PCI Full-Duplex Ethernet Controller with built-in SRAM |
| RTL80A125V1M9 | 制造商:OSLO SWITCH 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。