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參數(shù)資料
| 型號(hào)： | RTL8019AS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Realtek Full-Duplex Ethernet Controller with Plug and Play Function (RealPNP) |
| 中文描述： | 瑞昱全雙工以太網(wǎng)控制器即插即用功能（RealPNP） |
| 文件頁數(shù)： | 14/50頁 |
| 文件大?。?/td> | 992K |
| 代理商： | RTL8019AS |
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8019AS.doc
2001-05-10
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SPECIFICATION
RTL8019AS
14
TSR:
Transmit Status Register (04H; Type=R in Page0)
This register indicates the status of a packet transmission.
Bit
7
Symbol
OWC
Description
Out of Window Collision. It is set when a collision is detected after a slot time (51.2us).
Transmissions are rescheduled as in normal collisions.
CD Heartbeat. The NIC watches for a collision signal (i.e. CD Heartbeat signal) during
the first 6.4us of the interframe gap following a transmission. This bit is set if the
transceiver fails to send this signal.
Always 1.
Carrier Sense lost bit is set when the carrier is lost during transmitting a packet.
It indicates the NIC aborted the transmission because of excessive collisions.
It indicates the transmission collided with some other station on the network.
Always 1
This bit indicates the transmission completes with no errors.
6
CDH
5
4
3
2
1
0
-
CRS
ABT
COL
-
PTX
RCR:
Receive Configuration Register (0CH; Type=W in Page0, Type=R in Page2)
Bit
7
6
5
Symbol
-
-
MON
Description
Always 1
Always 1
When monitor mode bit is set, received packets are checked for address match, good CRC
and frame alignment but not buffered to memory. Otherwise, packets will be buffered to
memory.
If PRO=1, all packets with physical destination address accepted.
If PRO=0, physical destination address must match the node address programmed in
PAR0-5.
If AM=1, packets with multicast destination address are accepted.
If AM=0, packets with multicast destination address are rejected.
If AB=1, packets with broadcast destination address are accepted.
If AB=0, packets with broadcast destination address are rejected.
If AR=1, packets with length fewer than 64 bytes are accepted.
If AR=0, packets with length fewer than 64 bytes are rejected.
If SEP=1, packets with receive errors are accepted.
If SEP=0, packets with receive errors are rejected.
4
PRO
3
AM
2
AB
1
AR
0
SEP
RSR:
Receive Status Register (0CH; Type=R in Page0)
Bit
7
6
Symbol
DFR
DIS
Description
Defferring. Set when a carrier or a collision is detected.
Receiver Disabled. When the NIC enters the monitor mode, this bit is set and receiver is
disabled. Reset when receiver is enabled after leaving the monitor mode.
PHY bit is set when the received packet has a multicast or broadcast destination address. It
is reset when the received packet has a physical destination address.
Missed Packet bit is set when the incoming packet can not be accepted by NIC because of
a lack of receive buffer or if NIC is in monitor mode. Increment CNTR2 tally counter.
Always 1.
Frame Alignment Error bit reflects the incoming packet didn't end on a byte boundary
and CRC did not match at last byte boundary. Increment CNTR0 tally counter.
CRC error bit reflects packet received with CRC error. This bit will also be set for FAE
errors. Increment CNTR1 tally counter.
This bit indicates packet received with no errors.
CLDA0, 1:
Current Local DMA Registers (01H & 02H; Type=R in Page0)
These two registers can be read to get the current local DMA address.
5
PHY
4
MPA
3
2
-
FAE
1
CRC
0
PRX
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