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參數(shù)資料
| 型號： | RT9238CS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | VRM 8.5 PWM AND TRIPLE LINEAR POWER SYSTEM CONTROLLER |
| 中文描述： | VRM電源8.5脈寬調(diào)制和三線性電源系統(tǒng)控制器 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 434K |
| 代理商： | RT9238CS |
Preliminary
RT9238
DS9238-01 July 2001
www.richtek-ic.com.tw
13
MOSFET’s on-resistance, R
DS(ON)
to monitor the
current for protection against a shorted output. All
linear regulators monitor their respective VSEN pins
for under-voltage to protect against excessive
currents.
Fig.5 illustrates the over-current protection with an
overload on OUT1. The overload is applied at T0 and
the current increases through the inductor (L
OUT1
). At
time T1, the OC1 comparator trips when the voltage
across
Q1
(i
D
R
DS(ON)
)
programmed by R
OCSET
. This inhibits outputs 1, 2,
and 3, discharges the soft-start capacitor C
SS24
with
28
μ
A current sink, and increments the counter. Soft-
start capacitor C
SS13
is quickly discharged. C
SS13
starts ramping up at T2 and initiates a new soft-start
cycle. With OUT2 still overloaded, the inductor
current increases to trip the over-current comparator.
Again, this inhibits the outputs, but the C
SS24
soft-
start voltage continues increasing to above 4.0V
before discharging. Soft-start capacitor C
SS13
is,
again, quickly discharged. The counter increments to
2. The soft-start cycle repeats at T3 and trips the
over-current comparator. The SS24 pin voltage
increases to above 4.0V at T4 and the counter
increments to 3. This sets the fault latch to disable
the converter.
exceeds
the
level
Fig.5 Over-current Operation
The three linear controllers monitor their respective
VSEN pins for under-voltage. Should excessive
currents cause VSEN3 or VSEN4 to fall below the
linear under-voltage threshold, the respective UV
signals set the OC latch or the FAULT latch,
providing respective C
SS
capacitors are fully
charged. Blanking the UV signals during the C
SS
charge interval allows the linear outputs to build
above the under-voltage threshold during normal
operation. Cycling the bias input power off then on
resets the counter and the fault latch.
An external resistor (R
OCSET
) programs the over-
current trip level for the PWM converter. As shown in
Fig.6, the internal 200
μ
A current sink (I
OCSET
)
develops a voltage across R
OCSET
(V
SET
) that is
referenced to V
IN
. The DRIVE signal enables the
over-current comparator (OC). When the voltage
across the upper MOSFET (V
DS(ON)
) exceeds V
SET
,
the over-current comparator trips to set the over-
current latch. Both V
SET
and V
DS
are referenced to
V
IN
and a small capacitor across R
OCSET
helps
V
OCSET
track the variations of V
IN
due to MOSFET
switching. The over-current function will trip at a peak
inductor current (I
PEAK
) determined by:
The OC trip point varies with MOSFET’s R
DS(ON)
temperature variations. To avoid over-current tripping
in the normal operating load range, determine the
ROCSET resistor value from the equation above
with:
1. The maximum R
DS(ON)
at the highest junction
temperature
2. The minimum I
OCSET
from the specification table
3. Determine I
PEAK
for I
PEAK
> I
OUT(MAX)
+ (
I)/ 2,
where
I is the output inductor ripple current.
For an equation for the ripple current see the section
under component guidelines titled ‘Output Inductor
Selection’.
)
ON
(
DS
OCSET
OCSET
I
PEAK
I
R
R
×
=
0A
0V
2V
4V
0V
10V
F
S
S
I
2
1
T0T1
T2
T3T4
TIME
FAULT
REPORTED
COUNT = 1
COUNT = 2
COUNT = 3
OVERLOAD
APPLIED
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