參數(shù)資料
型號(hào)： RT9238CS
廠商： Electronic Theatre Controls, Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： VRM 8.5 PWM AND TRIPLE LINEAR POWER SYSTEM CONTROLLER
中文描述： VRM電源8.5脈寬調(diào)制和三線性電源系統(tǒng)控制器
文件頁(yè)數(shù)： 12/24頁(yè)
文件大?。?/td> 434K
代理商： RT9238CS
RT9238
Preliminary
www.richtek-ic.com.tw
12
DS9238-01 July 2001
Fig.3 Soft-start Interval
Fault Protection
All four outputs are monitored and protected against
extreme overload. The chip’s response to an output
overload is selective, depending on the faulting
output.
An over-voltage on V
OUT1
output (FB1) disables
outputs 1, 2, and 3, and latches the IC off. An under-
voltage on V
OUT4
output latches the IC off. A single
over-current event on output 1, or an under-voltage
event on output 2 or 3, increments the respective
fault counters and triggers a shutdown of outputs 1,
2, and 3, followed by a soft-start re-start. After three
consecutive fault events on either counter, the chip is
latched off. Removal of bias power resets both the
fault latch and the counters. Both counters are also
reset by a successful start-up of all the outputs.
Fig.3 shows a simplified schematic of the fault logic.
The over-current latches are set dependent upon the
states of the over-current (OC1), output 2 and 3
under-voltage (UV2, UV3) and the soft-start signals
(SS13, SS24). Window comparators monitor the SS
pins and indicate when the respective C
SS
pins are
fully charged to above 4.0V (UP signals). An under-
voltage on either linear output (VSEN2, VSEN3, or
VSEN4) is ignored until the respective UP signal
goes high. This allows V
OUT3
and V
OUT4
to increase
without fault at start-up. Following an over-current
event (OC1, UV2, or UV3 event), bringing the SS24
pin below 0.8V resets the over-current latch and
generates a soft-started ramp-up of the outputs 1, 2,
and 3.
Fig.4 Fault Logic-simplified Schematic
OUT1 Over-Voltage Protection
During operation, a short across the synchronous
PWM upper MOSFET (Q1) causes V
OUT1
to
increase. When the output exceeds the over-voltage
threshold of 115% of DACOUT, the over-voltage
comparator trips to set the fault latch and turns the
lower MOSFET (Q2) on. This blows the input fuse
and reduces V
OUT1
.
A separate over-voltage circuit provides protection
during the initial application of power. For voltages on
the VCC pin below the power-on reset (and above
~4V), the output level is monitored for voltages above
1.3V. Should FB1 exceed this level, the lower
MOSFET, Q2, is driven on.
Over-Current Protection
All outputs are protected against excessive over-
currents. The PWM controller uses the upper
+
_
+
_
+
_
S Q
R
S Q
R Q
R
S Q
COUNTER
R
COUNTER
SS13UP
UV3
OC1
4V
SS13
0.8V
SS24
OC
LATCH
SS24UP
4V
OV
UV4
UV2
OC
LATCH
POR
FAULT
LATCH
INHIBIT 1,2,3
SSDOWN
FAULT
R
0V
3.0V
0V
10V
T1
T2
T4T5
TIME
SS24
T0
T3
ATX12V
ATX5V
ATX3.3V
V
OUT4
(1.8V)
V
OUT3
(1.5V)
V
OUT2
(1.2V)
V
OUT1
(1.65V)
PGOOD
VTTPG
SS13
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