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型號：	RCB001
文件頁數(shù)：	879/1328頁
文件大?。?/td>	9519K
代理商：	RCB001

PRODUCT SPECIFICATION

The timing performance of the phase lock is controlled by an

external RC filter, the CSYNC signal, and internally-

generated horizontal sync signals. When the PLL is not

locked, CSYNC is selected as the reference input to the

phase detector. CSYNC is derived directly from the compos-

ite video input, which contains the required horizontal edge

information, and is not dependent upon the loop being

locked. When the loop is locked, an internally generated

horizontal sync signal from the timing generator is used for

this reference input. CSYNC is only used as the loop refer-

ence input in the unlocked condition, because it contains

serration pulses that would contribute undesirable jitter to

the VCO output.

The lock-detect output signal (HLOCK) indicates when the

phase reference and VCO inputs of the phase detector are

locked. The response time of the lock detector is controlled

by an external capacitor (C3) and, when lock is established,

the HLOCK output goes low and the MUX makes the appro-

priate reference signal choice. The value of C3 was chosen to

provide a lock-indication response time that is approxi-

mately 15 horizontal lines in duration, and an unlock-indica-

tion response time of approximately three horizontal lines in

duration. Increasing the value of C3 would result in increas-

ing both the lock and unlock response times.

The PLL consists of the phase detector, charge pump, loop

filter, VCO, and divide-by-N counter. The phase detector is

essentially a control loop summing junction. The charge

pump, loop filter, and VCO are in the forward path, and the

divide-by-N counter forms the feedback path. Stabilizing

this control system consists of choosing the proper compo-

nent values for the loop filter, such that sufficient phase mar-

gin exists at the unity-gain crossover frequency. The filter is

a lag-lead network formed by the charge pump, C1, R1, and

C2. Increasing the value of C1 moves the pole of the lag net-

work (low pass) closer to the origin (lower frequency). This

will reduce the loop bandwidth, which generally tends to

reduce VCO jitter, but at a cost of settling (response) time

and (in the extreme) stability. Table 2 shows values for R1,

C1, and C2 for all input setings.

Increasing the value of either R1 or C2 moves the zero of the

lead network (high pass) lower in frequency, which tends to

increase loop gain at higher frequencies and can also result

in poorer noise performance. The location of the zero is gen-

erally determined empirically to adjust the loop transfer

function for adequate phase margin for a given desired band-

width. The RC6100 loop settling time is approximately

s, and lock detection requires about one millisecond.

Figure 4. HRESET Output Timing

4ns < t1 < 11ns t2

Table 1. Clock Frequency Selection

Selection Codes

Frequencies (MHz) and Divisors (N)

NTSC (CCIR601)

NTSC (4fSC/Studio)

NTSC (Sq. Pixel)

PAL (CCIR601)

PAL (4fSC/Studio)

PAL (Sq. Pixel)

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
RCB001-12A	制造商:Rochester Electronics LLC 功能描述:- Bulk
RCB002	制造商:未知廠家制造商全稱:未知廠家功能描述:
RCB004	制造商:未知廠家制造商全稱:未知廠家功能描述:
RCB004-12	制造商:Rochester Electronics LLC 功能描述:- Bulk
RCB005	制造商:未知廠家制造商全稱:未知廠家功能描述:

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