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RC5040
PRODUCT SPECIFICATION
12
Figure 5. Charge Pump Configuration
PWM/PFM
Control
65-5040-13
+5V
L1
VCCQP
HIDRV
LODRV
GNDP
M1
CP
RS
DS1
DS2
CB
VO
.
Figure 6. R(DS) vs. V
GS
for Selected MOSFETs
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
1.5 2
2.5 3
3.5 4
5
6
7
8
9
10
11
V
GS
R
D
R(DS)Fuji
R(DS)Fuji
R(DS)706A
R(DS)-706AEL
,
where
Design Equations:
where
, where q
GATE
is the gate charge and f is the switching frequency
, where C
RSS
is the reverse transfer capacitance of the high-side MOSFET.
Efficiency
P
IN
-p
I
′
OUT
+
OUT
V
OUT
P
LOSS
I
=
=
P
LOSS
PD
MOSFET
PD
INDUCTOR
PD
RSENSE
PD
GATE
PD
DIODE
PD
TRAN
PD
CAP
PD
IC
+
+
+
+
+
+
+
=
(1) PD
MOSFET
I
OUT
2
R
DS ON
)
′
DutyCycle
′
=
DutyCycle
V
IN
V
D
V
SW
–
+
V
D
+
V
=
(2) PD
INDUCTOR
I
OUT
2
R
INDUCTOR
′
=
(3) PD
RSENSE
I
OUT
2
R
SENSE
′
=
(4) PD
GATE
q
GATE
f
5V
′
′
=
(5) PD
DIODE
V
f
I
OUT
′
1
Dutycycle
–
(
)
=
(6) PD
TRAN
V
--------------------I
2
C
DRIVE
I
LOAD
′
f
′
=
Converter Efficiency
Losses due to parasitic resistance in the switches, coil, and
sense resistor dominate at high load-current level. The major
loss mechanisms under heavy loads, in usual order of impor-
tance, are:
MOSFET I
2
R Losses
Inductor Coil Losses
Sense Resistor Losses
gate-charge losses
diode-conduction losses
transition losses
Input Capacitor losses
losses due to the operating supply current of the IC.
Efficiency of the converter under heavy loads can be calcu-
lated as follows: