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PRODUCT SPECIFICATION
RC5053
9
P
connected to OUTEN. Adjusting the oscillator frequency can
add flexibility in the external component selection. See the
Clock Synchronization section.
Output regulation can be monitored with the PWRGD pin
which in turn monitors the internal MIN and MAX compara-
tors. If the output is
±
5% beyond the selected value for more
than 500
μ
s, the PWRGD output will be pulled low. Once the
output has settled within
±
5% of the selected value for more
than 1ms, PWRGD will return high.
Theory of Operation
Primary Feedback Loop
The regulator output voltage at the SENSE pin is divided
down internally by a resistor divider with a total resistance of
approximately 120k
. This divided down voltage is sub-
tracted from a reference voltage supplied by the DAC output.
The resulting error voltage is amplified by the error amplifier
and the output is compared to the oscillator ramp waveform
by the PWM comparator. This PWM signal controls the
external MOSFETs through G1 and G2. The resulting
chopped waveform is filtered by L
O
and C
OUT
closing the
loop. Loop frequency compensation is achieved with an
external RC + C network at the COMP pin, which is con-
nected to the output node of the transconductance amplifier.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed fault correction in situations where the ERR
amplifier may not respond quickly enough. MIN compares
the feedback signal FB to a voltage 60mV (5%) below the
internal reference. If FB is lower than the threshold of this
comparator, the MIN comparator overrides the ERR ampli-
fier and forces the loop to full duty cycle which is set by the
internal oscillator typically to 82%. Similarly, the MAX
comparator forces the output to 0% duty cycle if FB is more
than 5% above the internal reference. To prevent these two
comparators from triggering due to noise, the MIN and MAX
comparators’ response times are deliberately controlled so
that they take two or three microseconds to respond. These
two comparators help prevent extreme output perturbations
with fast output transients, while allowing the main feedback
loop to be optimally compensated for stability.
Soft Start and Current Limit
The RC5053 includes a soft start circuit which is used for
initial start-up and during current limit operation. The SS pin
requires an external capacitor to SGND with the value deter-
mined by the required soft start time. An internal 10
μ
A cur-
rent source is included to charge the external SS capacitor.
During start-up, the COMP pin is clamped to a diode drop
above the voltage at the SS pin. This prevents the error
amplifier, ERR, from forcing the loop to maximum duty
cycle. The RC5053 will begin to operate at low duty cycle as
the SS pin rises above about 1.2V (V
COMP
≈
1.8V). As SS
continues to rise, Q
SS
turns off and the error amplifier begins
to regulate the output.The MIN comparator is disabled when
soft start is active to prevent it from overriding the soft start
function.
The RC5053 includes yet another feedback loop to control
operation in current limit. Just before every falling edge of
G1, the current comparator, CC, samples and holds the volt-
age drop measured across the external MOSFET, Q1, at the
I
FB
pin. CC compares the voltage at I
FB
to the voltage at the
I
MAX
pin. As the peak current rises, the measured voltage
across Q1 increases due to the drop across the R
DS(ON)
of
Q1.When the voltage at I
FB
drops below I
MAX
, indicating
that Q1’s drain current has exceeded the maximum level, CC
starts to pull current out of the external soft start capacitor,
cutting the duty cycle and controlling the output current
level. The CC comparator pulls current out of the SS pin in
proportion to the voltage difference between I
FB
and I
MAX
.
Under minor overload conditions, the SS pin will fall gradu-
ally, creating a time delay before current limit takes effect.
Very short, mild overloads may not affect the output voltage
at all. More significant overload conditions will allow the SS
pin to reach a steady state, and the output will remain at a
reduced voltage until the overload is removed. Serious over-
loads will generate a large overdrive at CC, allowing it to pull
SS down quickly and preventing damage to the output com-
ponents.
By using the R
DS(ON)
of Q1 to measure the output current,
the current limiting circuit eliminates an expensive discrete
sense resistor that would otherwise be required. This helps
minimize the number of components in the high current path.
Due to switching noise and variation of R
DS(ON)
, the actual
current limit trip point is not highly accurate. The current
limiting circuitry is primarily meant to prevent damage to the
power supply circuitry during fault conditions. The exact
current level where the limiting circuit begins to take effect
will vary from unit to unit as the R
DS(ON)
of Q1 varies.
For a given current limit level, the external resistor from
I
MAX
to V
IN
can be determined by:
where,
I
LMAX
I
LOAD
= Maximum load current;
I
RIPPLE
= Inductor ripple current
f
OSC
= RC5053 oscillator frequency = 300kHz
L
O
= Inductor value
R
DS(ON)Q1
= Hot on-resistance of Q1 at I
LMAX
I
IMAX
= Internal 180
μ
A sink current at I
MAX
R
IMAX
I
-----------------------------------------------------
(
)
R
I
IMAX
)
=
I
LOAD
I
2
-------------------
+
=
V
V
O
–
(
--------f
)
V
OUT
)
V
IN
(
(
)
OSC
(
)
=