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RC7105
PRODUCT SPECIFICATION
2
A
Pin Assignments
Pin Descriptions
Pin Name
SDRAM0:12
Pin Number
2, 3, 6, 7, 10, 11,
18, 19, 22, 23,
26, 27, 12
Type
OUT
Pin Function Description
SDRAM Outputs:
Provides buffered copy of BUF_IN. The
propagation delay from a rising input edge to a rising output
edge is 1 to 5ns. All outputs are skew controlled to within
±
250ps of each other.
Clock Input:
This clock input has an input threshold voltage of
1.5V (typ).
I
2
C Data input:
Data should be presented to this input as
described in the I
2
C section of this data sheet.
I
2
C clock input:
The I
2
C clock should be presented to this input
as described in the I
2
C section of this data sheet.
Power Connection:
Power supply for core logic and output
buffers. Connected to 3.3V supply.
Ground Connection:
Connect all ground pins to the common
system ground plane.
BUF_IN
9
IN
SDA
14
IN/OUT
SCL
15
IN
VDD
1, 5, 13, 20, 24,
28
4, 8, 16, 17, 21,
25
POWER
GND
GROUND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDD
SDRAM11
SDRAM10
GND
VDD
SDRAM9
SDRAM8
GND
VDD
SDRAM7
SDRAM6
GND
GND
SCL
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD
SDA