
RC7104
PRODUCT SPECIFICATION
12
A
Writing Data Bytes
Each bit of the 10 data bytes controls a particular device func-
tion except for the “reserved” bits. These must by preserved by
writing a logic 0. Bit 7, the MSB, is written first. See Table 4
for bit descriptions of Data Bytes 3–6.
Table 5 shows additional frequency selections that are program-
mable via the serial data interface.
Table 7 shows the mode select functions for Byte 3, bits 1 and 0.
Table 4. Data Bytes 3-6 Serial Configuration Map
Bit(s)
Data Byte 3
7
6
5
4
3
Affected Pin
Pin No.
Bit Control
Pin Name
Control Function
0
1
Default
—
—
—
—
—
—
—
—
—
(Reserved)
SEL_2
SEL_1
SEL_0
BYT0 _FS#
—
Refer to Table 5
Refer to Table 5
Refer to Table 5
Frequency
Controlled by
external SEL100/
66# pin
—
0
0
0
0
0
Frequency
Controlled by
BYT0 SEL (2:0)
2
1-0
—
—
(Reserved)
Bit 1
0
00
—
Bit 0
Function (See Table 7 for function
details)
Normal Operation
Test Mode
Spread Spectrum on (See Table 6 for
frequency & spread selections, when
Spread Spectrum is on. See Table 5
for frequency selections when Spread
Spectrum is off).
All Outputs Tristated
0
0
1
0
1
0
1
1
Data Byte 4
7
6
5
4
3
2
1
0
Data Byte 5
7
6
5
4
3
2
1
0
—
14
—
—
—
21
—
22
—
24/48MHz
—
—
—
CPU1
—
CPU0
(Reserved)
Clock Output disable
(Reserved)
(Reserved)
(Reserved)
Clock Output disable
(Reserved)
Clock Output disable
—
Low
—
—
—
Low
—
Low
—
Active
—
—
—
Active
—
Active
0
1
0
0
0
1
0
1
4
11
10
—
8
7
6
5
PCICLK_F
PCI6
PCI5
—
PCI4
PCI3
PCI2
PCI1
Clock Output disable
Clock Output disable
Clock Output disable
(Reserved)
Clock Output disable
Clock Output disable
Clock Output disable
Clock Output disable
Low
Low
Low
—
Low
Low
Low
Low
Active
Active
Active
—
Active
Active
Active
Active
1
1
1
0
1
1
1
1