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參數(shù)資料
| 型號： | RC28F160C3TC90 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA64 |
| 封裝： | BGA-64 |
| 文件頁數(shù)： | 30/72頁 |
| 文件大?。?/td> | 1083K |
| 代理商： | RC28F160C3TC90 |
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Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
36
Order Number: 290645, Revision: 023
8.5
Power and Reset Considerations
8.5.1
Power-Up/Down Characteristics
To prevent any condition that may result in a spurious write or erase operation, Intel recommends
to power-up VCC and VCCQ together. Conversely, VCC and VCCQ must power-down together.
Intel also recommends that you power-up VPP with or after VCC has reached VCCmin.
Conversely, VPP must powerdown with or slightly before VCC.
If VCCQ and/or VPP are not connected to the VCC supply, then VCC must attain VCCmin before
applying VCCQ and VPP. Device inputs must not be driven before supply voltage reaches
VCCmin.
Power supply transitions must only occur when RP# is low.
8.5.2
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system reads from the flash memory when it comes out of reset. If a CPU reset occurs without a
flash memory reset, proper CPU initialization will not occur because the flash memory may be
providing status information instead of array data. Intel recommends connecting RP# to the system
CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when VCC voltages are above VLKO. Because
both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs.
By holding the device in reset during power-up/down, invalid bus conditions during power-up can
be masked, providing yet another level of memory protection.
8.5.3
VCC, VPP and RP# Transitions
The CUI latches commands as issued by system software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
VCC transitions above VLKO (Lockout voltage), is read-array mode.
After any program or Block-Erase operation is complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read-array mode by the Read Array command if access to the
flash-memory array is desired.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RC28F160C3TD70 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3) |
| RC28F160C3TD70A | 功能描述:IC FLASH 16MBIT 70NS 64BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| RC28F160C3TD70B | 制造商:Micron Technology Inc 功能描述:16MB, ARMAGOSA EBGA 3.0 |
| RC28F256J3A-110 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| RC28F256J3A-115 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
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