參數(shù)資料
型號: R5F562N8BDFP#V0
廠商: Renesas Electronics America
文件頁數(shù): 77/148頁
文件大?。?/td> 0K
描述: MCU 32BIT FLASH 512K ROM 100LQFP
產(chǎn)品培訓模塊: RX USB Peripheral
CAN Peripheral and API
RX 12-Bit ADC
RX Bus State Controller
RX Low Voltage Detection and Reset Sources
RX Watchdog Timer
RX 10-Bit ADC
RX 10-Bit DAC
RX Core
RX Compare Match Timer
RX DMAC
特色產(chǎn)品: RX600 Series Microcontrollers
標準包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,SCI,SPI,USB
外圍設備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 72
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10/12b,D/A 1x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 32
2004 Microchip Technology Inc.
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET
Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
PIC18F6X20 PIC18F8X20
---0 0000
---0 uuuu(3)
TOSH
PIC18F6X20 PIC18F8X20
0000 0000
uuuu uuuu(3)
TOSL
PIC18F6X20 PIC18F8X20
0000 0000
uuuu uuuu(3)
STKPTR
PIC18F6X20 PIC18F8X20
00-0 0000
uu-0 0000
uu-u uuuu(3)
PCLATU
PIC18F6X20 PIC18F8X20
---0 0000
---u uuuu
PCLATH
PIC18F6X20 PIC18F8X20
0000 0000
uuuu uuuu
PCL
PIC18F6X20 PIC18F8X20
0000 0000
PC + 2(2)
TBLPTRU
PIC18F6X20 PIC18F8X20
--00 0000
--uu uuuu
TBLPTRH
PIC18F6X20 PIC18F8X20
0000 0000
uuuu uuuu
TBLPTRL
PIC18F6X20 PIC18F8X20
0000 0000
uuuu uuuu
TABLAT
PIC18F6X20 PIC18F8X20
0000 0000
uuuu uuuu
PRODH
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
PRODL
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
INTCON
PIC18F6X20 PIC18F8X20
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
PIC18F6X20 PIC18F8X20
1111 1111
uuuu uuuu(1)
INTCON3
PIC18F6X20 PIC18F8X20
1100 0000
uuuu uuuu(1)
INDF0
PIC18F6X20 PIC18F8X20
N/A
POSTINC0
PIC18F6X20 PIC18F8X20
N/A
POSTDEC0
PIC18F6X20 PIC18F8X20
N/A
PREINC0
PIC18F6X20 PIC18F8X20
N/A
PLUSW0
PIC18F6X20 PIC18F8X20
N/A
FSR0H
PIC18F6X20 PIC18F8X20
---- xxxx
---- uuuu
FSR0L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
WREG
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
INDF1
PIC18F6X20 PIC18F8X20
N/A
POSTINC1
PIC18F6X20 PIC18F8X20
N/A
POSTDEC1
PIC18F6X20 PIC18F8X20
N/A
PREINC1
PIC18F6X20 PIC18F8X20
N/A
PLUSW1
PIC18F6X20 PIC18F8X20
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4:
See Table 3-2 for Reset value for specific condition.
5:
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6:
Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
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