參數(shù)資料
型號: R5F562N8BDFP#V0
廠商: Renesas Electronics America
文件頁數(shù): 141/148頁
文件大?。?/td> 0K
描述: MCU 32BIT FLASH 512K ROM 100LQFP
產品培訓模塊: RX USB Peripheral
CAN Peripheral and API
RX 12-Bit ADC
RX Bus State Controller
RX Low Voltage Detection and Reset Sources
RX Watchdog Timer
RX 10-Bit ADC
RX 10-Bit DAC
RX Core
RX Compare Match Timer
RX DMAC
特色產品: RX600 Series Microcontrollers
標準包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,以太網,I²C,SCI,SPI,USB
外圍設備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 72
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10/12b,D/A 1x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 90
2004 Microchip Technology Inc.
REGISTER 9-2:
INTCON2 REGISTER
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1
= All PORTB pull-ups are disabled
0
= PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 3
INTEDG3: External Interrupt 3 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
bit 1
INT3IP: INT3 External Interrupt Priority bit
1
= High priority
0
= Low priority
bit 0
RBIP: RB Port Change Interrupt Priority bit
1
= High priority
0
= Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
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