參數(shù)資料
型號(hào)： R5F56218BDLE#U0
廠商： Renesas Electronics America
文件頁數(shù)： 52/148頁
文件大?。?/td> 0K
描述： MCU 32BIT FLASH 512KROM 145TFLGA
產(chǎn)品培訓(xùn)模塊： RX Compare Match Timer
RX DMAC
標(biāo)準(zhǔn)包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： CAN，EBI/EMI，I²C，SCI，SPI，USB
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 103
程序存儲(chǔ)器容量： 512KB（512K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 2x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 145-TFLGA
包裝： 托盤
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 144
2004 Microchip Technology Inc.
14.1
Timer3 Operation
Timer3 can operate in one of these modes:
As a timer
As a synchronous counter
As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored and the pins are read as ‘0’.
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see Section 14.0
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
TMR3H
TMR3L
T1OSC
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN
Enable
Oscillator(1)
TMR3IF
Overflow
Interrupt
FOSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
1
Synchronized
Clock Input
2
T1OSO/
T1OSI
Flag bit
(3)
Note 1:
When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T13CKI
CLR
CCP Special Trigger
T3CCPx
Timer3
TMR3L
T1OSC
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
1
Synchronized
Clock Input
2
T1OSO/
T1OSI
TMR3
T13CKI
CLR
CCP Special Trigger
T3CCPx
To Timer1 Clock Input
Note 1:
When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR3H
8
Read TMR3L
Write TMR3L
Set TMR3IF Flag bit
on Overflow
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