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參數(shù)資料
| 型號： | R5F56218BDLE#U0 |
| 廠商： | Renesas Electronics America |
| 文件頁數(shù)： | 110/148頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT FLASH 512KROM 145TFLGA |
| 產(chǎn)品培訓(xùn)模塊： | RX Compare Match Timer RX DMAC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | RX600 |
| 核心處理器： | RX |
| 芯體尺寸： | 32-位 |
| 速度： | 100MHz |
| 連通性： | CAN，EBI/EMI，I²C，SCI，SPI，USB |
| 外圍設(shè)備： | DMA，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 103 |
| 程序存儲器容量： | 512KB（512K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 96K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10/12b，D/A 2x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 145-TFLGA |
| 包裝： | 托盤 |
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PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 62
2004 Microchip Technology Inc.
FIGURE 5-2:
TABLE WRITE OPERATION
5.2
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
5.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit EEPGD determines if the access will be a
program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
Control bit CFGS determines if the access will be to the
configuration/calibration
registers,
or
to
program
memory/data EEPROM memory. When set, subse-
quent operations will operate on configuration regis-
ters, regardless of EEPGD (see Section 23.0 “Special
Features of the CPU”). When clear, memory selection
access is determined by EEPGD.
The FREE bit, when set, will allow a program memory
erase operation. When the FREE bit is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR), due to Reset values of zero.
The WR control bit, initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation. The
inability to clear the WR bit in software prevents the
accidental
or
premature
termination
of
a
write
operation.
Table Pointer(1)
Table Latch (8-bit)
TBLPTRH
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1:
Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in
Holding Registers
Program Memory
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.
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