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參數(shù)資料
| 型號(hào)： | R5F56218BDLE#U0 |
| 廠商： | Renesas Electronics America |
| 文件頁(yè)數(shù)： | 20/148頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT FLASH 512KROM 145TFLGA |
| 產(chǎn)品培訓(xùn)模塊： | RX Compare Match Timer RX DMAC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | RX600 |
| 核心處理器： | RX |
| 芯體尺寸： | 32-位 |
| 速度： | 100MHz |
| 連通性： | CAN，EBI/EMI，I²C，SCI，SPI，USB |
| 外圍設(shè)備： | DMA，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 103 |
| 程序存儲(chǔ)器容量： | 512KB（512K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 96K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10/12b，D/A 2x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 145-TFLGA |
| 包裝： | 托盤 |
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PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 114
2004 Microchip Technology Inc.
10.5
PORTE, TRISE and LATE
Registers
PORTE is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with the CCP module
On PIC18F8X20 devices, PORTE is also multiplexed
with the system bus as the external memory interface;
the I/O bus is available only when the system bus is
disabled, by setting the EBDIS bit in the MEMCON
register (MEMCON<7>). If the device is configured in
Microprocessor or Extended Microcontroller mode,
then the PORTE<7:0> becomes the high byte of the
address/data bus for the external program memory
interface. In Microcontroller mode, the PORTE<2:0>
pins become the control inputs for the Parallel Slave
Port when bit PSPMODE (PSPCON<4>) is set. (Refer
Modes” for more information on program memory
modes.)
When the Parallel Slave Port is active, three PORTE
pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10)
function as its control inputs. This automatically occurs
when the PSPMODE bit (PSPCON<4>) is set. Users
must also make certain that bits TRISE<2:0> are set to
configure the pins as digital inputs and the ADCON1
register is configured for digital I/O. The PORTE PSP
control functions are summarized in Table 10-9.
Pin RE7 can be configured as the alternate peripheral
pin for CCP module 2 when the device is operating in
Microcontroller mode. This is done by clearing the
configuration bit, CCP2MX, in configuration register,
CONFIG3H (CONFIG3H<0>).
EXAMPLE 10-5:
INITIALIZING PORTE
Note:
For PIC18F8X20 (80-pin) devices operat-
ing in Extended Microcontroller mode,
PORTE defaults to the system bus on
Power-on Reset.
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
MOVLW
0x03
; Value used to
; initialize data
; direction
MOVWF
TRISE
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
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