
R2043K/T
O
Control Register 2 (Address Fh)
D7
D6
VDSL
VDET
VDSL
VDET
0
0
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0v.
(1) VDSL
VDD Supply Voltage Monitoring Threshold Selection Bit
VDSL
Description
0
Selecting the VDD supply voltage monitoring threshold setting of
1.6v.
1
Selecting the VDD supply voltage monitoring threshold setting of
1.3v.
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
(2) VDET
Supply Voltage Monitoring Result Indication Bit
VDET
Description
0
Indicating supply voltage above the supply voltage monitoring
threshold settings.
1
Indicating supply voltage below the supply voltage monitoring
threshold settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will
hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage
monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.
(3) /XST
Oscillation Halt Sensing Monitor Bit
/XST
Description
0
Sensing a halt of oscillation
1
Sensing a normal condition of oscillation
The /XST accepts the reading and writing of 0 and 1. The /XST bit will be set to 0 when the oscillation halt
sensing. The /XST bit will hold 0 even after the restart of oscillation.
(4) PON
Power-on-reset Flag Bit
PON
Description
0
Normal condition
1
Detecting VDD power-on -reset
The PON bit is for sensing power-on reset condition.
*
The PON bit will be set to 1 when VDD power-on from 0v. The PON bit will hold the setting of 1
even after power-on.
*
When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control
Register 1, and Control Register 2, except /XST and PON. As a result, /INTR pin stops outputting.
*
The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.
(5) /CLEN1
32kHz Clock Output Bit 1
/CLEN1
Description
0
Enabling the 32-kHz clock circuit
1
Disabling the 32-kHz clock circuit
Setting the /CLEN1 bit or the /CLEN2 bit (D4 in the control register 1) to 0, specifies generating clock pulses
with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
Conversely, setting both the /CLEN1 and /CLEN2 bit to 1 disabling (”H”) such output.
12345
Rev.2.06 - 14 -
D5
/XST
/XST
Indefinite
D4
PON
PON
1
D3
/CLEN1
/CLEN1
0
D2
CTFG
CTFG
0
D1
WAFG
WAFG
0
D0
DAFG
DAFG
0
(For Writing)
(For Reading)
Default Settings *)
(Default)
(Default)
(Default)
(Default)