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參數(shù)資料
| 型號： | R2025S |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | High precision I2C-Bus Real-Time Clock Module |
| 中文描述： | REAL TIME CLOCK, PDSO14 |
| 封裝： | 10.10 X 7.40 MM, 3.10 MM HEIGHT, SOP-14 |
| 文件頁數(shù)： | 36/47頁 |
| 文件大小： | 524K |
| 代理商： | R2025S |
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R2025S/D
*1) Pulse Mode:
second
counter as illustrated in the timing chart below.
36
2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the
/INTRA Pin
Rewriting of the second counter
CTFG Bit
Approx. 92
μ
s
(Increment of second counter)
In the pulse mode, the increment of the second counter is delayed by approximately 92
μ
s from the
falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses
may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the
second counter will reset the other time counters of less than 1 second, driving the /INTRA pin low.
*2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1
minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second
are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
CTFG Bit
/INTRA Pin
Setting CTFG bit to 0
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
(Increment of
second counter)
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as
follows:
Pulse Mode:
The “L” period of output pulses will increment or decrement by a maximum of
±
3.784ms. For
example, 1-Hz clock pulses will have a duty cycle of 50
±
0.3784%.
Level Mode:
A periodic interrupt cycle of 1 second will increment or decrement by a maximum of
±
3.784
ms.
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