參數(shù)資料
型號(hào)： R2025S
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： High precision I2C-Bus Real-Time Clock Module
中文描述： REAL TIME CLOCK, PDSO14
封裝： 10.10 X 7.40 MM, 3.10 MM HEIGHT, SOP-14
文件頁(yè)數(shù)： 12/47頁(yè)
文件大?。?/td> 524K
代理商： R2025S
R2025S/D
(5) CT2,CT1, and CT0
CT2
12
Periodic Interrupt Selection Bits
CT0
Wave form
mode
0
-
1
-
0
Pulse Mode
*1)
1
Pulse Mode
*1)
0
Level Mode
*2)
1
Level Mode
*2)
0
Level Mode
*2)
1
Level Mode
*2)
Description
Interrupt Cycle and Falling Timing
CT1
0
0
0
0
0
1
OFF(H)
Fixed at “L”
2Hz(Duty50%)
(Default)
0
1
1Hz(Duty50%)
1
0
Once per 1 second (Synchronized with
second counter increment)
Once per 1 minute (at 00 seconds of
every minute)
Once per hour (at 00 minutes and 00
seconds of every hour)
Once per month (at 00 hours, 00
minutes,
and 00 seconds of first day of every
month)
1
0
1
1
1
1
* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second
counter as illustrated in the timing chart below.
/INTRA Pin
Rewriting of the second counter
CTFG Bit
Approx. 92
μ
s
(Increment of second counter)
In the pulse mode, the increment of the second counter is delayed by approximately 92
μ
s from the falling
edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may
appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the
second counter will reset the other time counters of less than 1 second, driving the /INTRA pin low.
* 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1
minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second
are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
CTFG Bit
/INTRA Pin
Setting CTFG bit to 0
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
(Increment of
second counter)
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