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參數資料
| 型號： | R2025S |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | High precision I2C-Bus Real-Time Clock Module |
| 中文描述： | REAL TIME CLOCK, PDSO14 |
| 封裝： | 10.10 X 7.40 MM, 3.10 MM HEIGHT, SOP-14 |
| 文件頁數： | 34/47頁 |
| 文件大小： | 524K |
| 代理商： | R2025S |
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R2025S/D
Alarm and Periodic Interrupt
34
The R2025S/D incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to
generate alarm signals and periodic interrupt signals, respectively, for output from the /INTRA or /INTRB pins as
described below.
(1) Alarm Interrupt Circuit
The alarm interrupt circuit is configured to generate alarm signals for output from the /INTRA or /INTRB, which is
driven low (enabled) upon the occurrence of a match between current time read by the time counters (the
day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers
intended for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and
minute digit settings). The Alarm_W is output from the /INTRB, and the Alarm_D is output from /INTRA.
(2) Periodic Interrupt Circuit
The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in
the level mode for output from the /INTRA pin depending on the CT2, CT1, and CT0 bit settings in the control
register 1.
The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in
the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits
in the Control Register 1) as listed in the table below.
Flag bits
Enable bits
Output
Pin
/INTRB
Alarm_
W
WAFG
(D1 at Address
Fh)
DAFG
(D0 at Address
Fh)
CTFG
(D2 at Address
Fh)
WALE
(D7 at Address Eh)
Alarm_D
DALE
(D6 at Address Eh)
/INTRA
Peridic
Interrupt
CT2=CT1=CT0=0
(These bit setting of “0” disable the Periodic
Interrupt)
(D2 to D0 at Address Eh)
/INTRA
* At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1, the
/INTRA and /INTRB pins are driven high (disabled).
* When two types of interrupt signals are output simultaneously from the /INTRA pin, the output from the
/INTRA pin becomes an OR waveform of their negative logic.
Example: Combined Output to /INTRA Pin Under Control of
/ALARM_D and Periodic Interrupt
In this event, which type of interrupt signal is output from the /INTRA pin can be confirmed by reading the
DAFG, and CTFG bit settings in the Control Register 2.
Alarm Interrupt
Periodic Interrupt
/INTRA
/Alarm_D
The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1)
and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to enable
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