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參數(shù)資料
| 型號： | R2025S |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | High precision I2C-Bus Real-Time Clock Module |
| 中文描述： | REAL TIME CLOCK, PDSO14 |
| 封裝： | 10.10 X 7.40 MM, 3.10 MM HEIGHT, SOP-14 |
| 文件頁數(shù)： | 23/47頁 |
| 文件大小： | 524K |
| 代理商： | R2025S |
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R2025S/D
23
(3) Data Transmission Format in I
2
C-Bus
I
2
C-Bus has no chip enable signal line. In place of it, each device has a 7bit Slave Address allocated. The first
1byte is allocated to this 7bit address and to the command (R/W) for which data transmission direction is
designated by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2 and
after bytes are read, when 8bit is “H” and when write “L”.
The Slave Address of the R2025S/D is specified at (0110010).
At the end of data transmission / receiving, Stop Condition is generated to complete transmission. However, if
start condition is generated without generating Stop Condition, Repeated Start Condition is met and transmission /
receiving data may be continue by setting the Slave Address again. Use this procedure when the transmission
direction needs to be change during one transmission.
Data is written to the slave
from the master
S
A
A
Data
/A P
S
0
A
Slave Address
Data
A
A P
When data is read from the
slave immediately after 7bit
addressing from the master
Master to slave
Slave to master
Sr
Repeated Start Condition
P
Stop Condition
A
A
/AAcknowledge Signal
R/W=1(Read)
(0110010)
Inform read has been completed by not generate
an acknowledge signal to the slave side.
Data
R/W=0(Write)
(0110010)
When
direction is to be changed
during transmission.
the
transmission
Sr
1
0
A
A
R/W=0(Write)
A
Data
R/W=1(Read)
(0110010)
S
1
A
/A P
Inform read has been completed by not generate
an acknowledge signal to the slave side.
Data
S
Start Condition
(0110010)
Slave Address
Salve Address
Slave Address
Data
Data
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