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參數(shù)資料
| 型號： | R2023T |
| 廠商： | Ricoh Co., Ltd. |
| 英文描述： | 2-wire Serial Interface Real Time Clock IC |
| 中文描述： | 2線串行接口實時時鐘芯片 |
| 文件頁數(shù)： | 39/50頁 |
| 文件大?。?/td> | 512K |
| 代理商： | R2023T |
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R2023K/T
Alarm and Periodic Interrupt
39
The R2023K/T incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to
generate alarm signals and periodic interrupt signals for output from the INTRA or INTRB pin as described
below.
(1) Alarm Interrupt Circuit
The alarm interrupt circuit is configured to generate alarm signals for output from the INTRA or INTRB , which
is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the
day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers
intended for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and
minute digit settings). The Alarm_W is output from the INTRB pin, the Alarm_D is output from INTRA pin.
(2) Periodic Interrupt Circuit
The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in
the level mode for output from the INTRA pin depending on the CT2, CT1, and CT0 bit settings in the control
register 1.
The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the
Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in
the Control Register 1) as listed in the table below.
Flag bits
Enable bits
Alarm_W
WAFG
(D1 at Address
Fh)
Alarm_D
DAFG
(D0 at Address
Fh)
Peridic
interrupt
(D2 at Address
Fh)
nterrupt)
(D2 to D0 at Address Eh)
* At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1,
the INTRA or INTRB pin is driven high (disabled).
* When two types of interrupt signals are output simultaneously from the INTRA pin, the output from the
INTRA pin becomes an OR waveform of their negative logic.
Output Pin
INTRB
WALE
(D7 at Address Eh)
DALE
(D6 at Address Eh)
INTRA
CTFG
CT2=CT1=CT0=0
(These bit setting of “0” disable the Periodic
INTRA
In this event, which type of interrupt signal is output from the INTRA pin can be confirmed by reading the
DAFG, and CTFG bit settings in the Control Register 2.
Alarm Interrupt
Example: Combined Output to INTRA Pin Under Control of
ALARM_D and Periodic Interrupt
Periodic Interrupt
INTRA
Alarm_D
The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1)
and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to enable
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相關(guān)代理商/技術(shù)參數(shù) |
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| R2023T-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:2-wire Serial Interface Real Time Clock IC |
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| R2025S | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:High precision I2C-Bus Real-Time Clock Module |
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