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| 型號(hào)： | QL82SD-PT280 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| 中文描述： | 10高速總線LVDS串行鏈路的帶寬高達(dá)5Gbps的 |
| 文件頁數(shù)： | 37/60頁 |
| 文件大?。?/td> | 3838K |
| 代理商： | QL82SD-PT280 |
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2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
37
www.quicklogic.com
There are 36 RAM blocks within the QuickSD device, for a total of 82.9 Kbits of RAM. Using
two "mode" pins, designers can configure each module into 128 x 18 (Mode 0), 256 x 9
(Mode 1), 512 x 4 (Mode 2), or 1024 x 2 blocks (Mode 3). The blocks are also easily
cascadable to increase their effective width and/or depth. See
Figure 47
for cascaded RAM
modules.
Figure 47: Cascaded RAM Modules
The RAM modules are dual-port, with completely independent READ and WRITE ports and
separate READ and WRITE clocks. The READ ports support asynchronous and synchronous
operation, while the WRITE ports support synchronous operation. Each port has 18 data
lines and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up
to 1,024 words. Depending on the mode selected, however, some higher order data or
address lines may not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation.
The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD
input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input
high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in
single modules by connecting corresponding address lines together and dividing the words
between modules.
A similar technique can be used to create depths greater than 512 words. In this case address
signals higher than the ninth bit are encoded onto the write enable (WE) input for WRITE
operations. The READ data outputs are multiplexed together using encoded higher READ
address bits for the multiplexer SELECT signals.
The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO
functions). The RAM achieve 155 MHz performance for the lowest speed grade devices
when using multiple blocks cascaded together.
Multiple Accessing of Memories
The extremely fast RAM can be used in designs that require multiple memory accessing. The
RAM achieves 280 MHz performance for the fastest speed grade and 155 MHz
performance for the lowest speed grade devices when using multiple blocks cascaded
together. Write through of DATA is also possible with the QuickLogic RAM.
WDATA
WADDR
WDATA
RDATA
RADDR
RDATA
RAM
Module
(2304 bits)
RAM
Module
(2304 bits)
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