參數(shù)資料
型號： QL82SD-PT280
廠商： Electronic Theatre Controls, Inc.
英文描述： 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps
中文描述： 10高速總線LVDS串行鏈路的帶寬高達5Gbps的
文件頁數(shù)： 34/60頁
文件大?。?/td> 3838K
代理商： QL82SD-PT280
www.quicklogic.com
2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
34
t
DD
is the delay from the rising edge of the start bit in the serial bitstream to the rising
edge of the recovered parallel clock
t
RXPD
is the propagation delay time provided for the recovered data with respect to the
recovered clock.
Transmit 8-bit Data With Channel Clock
When the SERDES is in 8-bit mode, it must be configured to use a channel clock. The
waveforms shown in
Figure 21
show the parallel transmit clock provided by the user to the
clock channel (ClkX_txclk), and the converted channel clock on the LVDS outputs of the
channel clock (pad_ClkX_p and pad_ClkX_n).
NOTE:
The output of the channel clock has the same period as the parallel transmit clock.
This is done to frame the serial data transmitted on the pad_ChX_p and pad_ChX_n pins.
The LVDS channel clock (pad_ClkX_p and pad_ClkX_n) is multiplied up by the receiver to
capture each bit of the transmitted data.
The 8-bit data is converted to a simple serial bit stream.
The pertinent timing parameters shown in
Figure 21
are:
t
DIS
is the setup time needed on the parallel transmit data (ChX_txd[7:0] with respect to
the parallel transmit clock (ClkX_txclk)
t
DIH
is the hold time needed on the parallel transmit data (ChX_txd[7:0] with respect to
the parallel transmit clock (ClkX_txclk)
t
SD
is the clock delay between the rising edge of the parallel transmit clock to the rising
edge of the LVDS channel clock
t
TXD[N-1]
is the serial data physical bit position with respect to the LVDS channel clock.
NOTE:
t
TXD[N-1]
denotes physical bit positions wrt pad_ClkX_p/n while pad_ChX_p/n bit[n]
refers to logical bit positions wrt ChX_txd[7:0].
Receive 8-bit Data With Channel Clock
The SERDES in 8-bit receive mode receives serial data on the pad_ChX_p and pad_ChX_n
LVDS input, and a clock on the pad_ClkX_p and pad_ClkX_n LVDS input (see
Figure 26
).
The LVDS input clock is multiplied by 8 within the SERDES core to capture the 8 bits of data
from the pad_ChX_p and pad_ChX_n serial bitstream. The parallelized data goes out on the
ChX_rxd internal 8-bit bus, and the re-timed parallel clock goes out on the ClkX_rxclk pin.
The pertinent timing parameters shown in this diagram are:
t
DD
is the delay between the first bit of the serial data showing up in the serial bit stream
and the rising edge of the retimed parallel clock corresponding to the same data frame
t
RXPD
is the propagation delay time provided for the recovered data with respect to the
recovered clock
t
RXDS
is the setup time needed for the serial data on the pad_ChX_p and pad_ChX_n
LVDS inputs to the rising edge of the internal serial clock strobe
t
RXDH
is the hold time needed for the serial data on the pad_ChX_p and pad_ChX_n
LVDS inputs relative to the internal serial clock strobe
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