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參數(shù)資料
| 型號： | QL82SD-PT280 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| 中文描述： | 10高速總線LVDS串行鏈路的帶寬高達5Gbps的 |
| 文件頁數(shù)： | 33/60頁 |
| 文件大?。?/td> | 3838K |
| 代理商： | QL82SD-PT280 |
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2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
33
www.quicklogic.com
Any data channel can also be configured as a level translator. This is done by setting that data
channel's ChX_mode[3:0] input to point to a channel clock (A or B) which has also been
configured in level translator mode.
LVDS SERDES Transmit and Receive Operation
The SERDES core can transmit and receive serial data across LVDS wires in many different
formats. This section describes each of the various transmit and receive formats.
Transmit 10-bit Data With Embedded Clock
The waveform in
Figure 19
, illustrates how 10-bit data can be transmitted serially on the
differential LVDS outputs.
NOTE:
The pad_ChX_p and pad_ChX_n outputs in the diagram are representing the data
changes which occur on a pair of LVDS signals.
When the SERDES is in 10-bit mode, no separate clock signal is needed, since the clock is
embedded within the serial data stream. In
Figure 19
, you will notice that at
t
DIS
the rising
edge of ChX_txclk registers the 10-bit data value B within the SERDES core. After about one
clock period of ChX_txclk, the serialized data begins to appear on the LVDS outputs
(pad_ChX_p and pad_ChX_n) in the following sequence:
1.
First, a logic 1 is transmitted, which is the start bit, and part of the data used to transmit
the clock.
2.
Then each of the 10 bits of the data value B is transmitted in sequence.
3.
Finally, a logic 0 is transmitted, which is the stop bit (MSB first). This stop bit is the
remaining part of the embedded clock.
NOTE:
By using a stop bit value of 0 and a start bit value of 1, there is always a guaranteed
0 to 1 transition in the bitstream (the end of one frame and the beginning of the next).
Because of this, the receiver is able to recover the embedded clock from the serial bit stream.
The pertinent timing parameters shown in
Figure 19
are:
t
DIS
is the setup time needed for the ChX_txd bus relative to the ChX_txclk clock
t
DIH
is the hold time for the ChX_txd relative to the ChX_txclk clock
Receive 10-bit Data With Embedded Clock
In 10-bit mode, the clock is embedded in the serial data stream on the pad_ChX_p and
pad_ChX_n LVDS signal (shown in
Figure 23
) as one signal, but actually is a pair of
differential signals). When using the SERDES data channel in 10-bit receive mode, a
reference clock is needed which matches the parallel clock rate of the transmitter (shown in
Figure 23
as ChX_txclk). There is no timing phase relationship between the reference clock
and the received parallel clock (ChX_rxclk), but the two clocks will have the same frequency.
NOTE:
The serial data bits are transmitted with a 0 as a stop bit and a 1 as a start bit, and.
The SERDES block recovers the clock from this data stream, as shown with the ChX_rxclk
waveform (
Figure 23
). The parallel 10-bit data is also recovered and timed appropriately with
the recovered clock.
The pertinent timing parameters shown in
Figure 23
are:
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