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參數(shù)資料
| 型號(hào)： | QL80FC-APB456I |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大小： | 757K |
| 代理商： | QL80FC-APB456I |
11
QL80FC - QuickFC
TM
QL80FC External Device Pins
*See QuickNote 65 on the QuickLogic web site for
information on RAM initialization.
QL80FC E
XTERNAL
D
EVICE
P
INS
Type
IN
Description
Input. A standard input-only
signal.
Totem pole output. A standard
active output driver.
Tri-state. A bi-directional, tri-state
input/output pin.
Sustained Tri-state. An active low
tri-state signal driven by one PCI
agent at a time. It must be driven
high for at least one clock before
being disabled (set to Hi-Z). A pull-
up needs to be provided by the
PCI system central resource to
sustain the inactive state once the
active driver has released the sig-
nal.
Open Drain. Allows multiple
devices to share this pin as a
wired-or.
OUT
T/S
S/T/S
O/D
Pin/Bus
Name
VCC
VCCIO
Type
Function
IN
IN
Supply pin. Tie to 3.3V supply.
Supply pin for I/O. Set to 3.3V for
3.3V I/O, 5V for 5.0V compliant I/O.
Ground pin. Tie to GND on the PCB.
Programmable Input/Output/Tri-State/
Bi-directional Pin.
Programmable Global Network or
Input-only pin. Tie to VCC or GND if
unused.
Programmable Array Network or Input-
only pin. Tie to VCC or GND if unused.
JTAG Data In/Ram Init. Serial Data In.
Tie to VCC if unused. Connect to Serial
EPROM data for RAM init.
JTAG Data Out/Ram Init Clock. Leave
unconnected if unused. Connect to
Serial EPROM clock for RAM init.
JTAG Clock. Tie to GND if unused.
JTAG Test Mode Select. Tie to VCC if
unused.
JTAG Reset/RAM Init. Reset Out. Tie
to GND if unused. Connect to Serial
EPROM reset for RAM init.
QuickLogic Reserved pin. Tie to GND
on the PCB.
GND
I/O
IN
T/S
GLCK/I
IN
ACLK/I
IN
TDI/
RSI*
IN
TDO/
RCO*
OUT
TCK
TMS
IN
IN
TRSTB/
RRO*
IN
STM
IN
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