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參數(shù)資料
| 型號： | QL80FC-APB456I |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 757K |
| 代理商： | QL80FC-APB456I |
10
Preliminary
10
QL80FC - QuickFC
TM
The Write Enable (WE) line acts as a clock enable for
synchronous write operation. The Read Enable (RE)
acts as a clock enable for synchronous READ opera-
tion (ASYNCRD input low), or as a flow-through
enable for asynchronous READ operation (ASYN-
CRD input high).
FIGURE 5. RAM Module
Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules. This
approach allows up to 512-deep configurations as
large as 16 bits wide in the QL80FC device.
A similar technique can be used to create depths
greater than 512 words. In this case, address signals
higher than the eighth bit are encoded onto the write
enable (WE) input for WRITE operations. The READ
data outputs are multiplexed together using encoded
higher READ address bits for the multiplexer
SELECT signals.
JTAG Support
JTAG pins support IEEE standard 1149.1a to pro-
vide boundary scan capability for the QL80FC
device. Six pins are dedicated to JTAG and program-
ming functions on each QL80FC device, and are
unavailable for general design input and output sig-
nals. TDI, TDO, TCK, TMS, and TRSTB are JTAG
pins. A sixth pin, STM, is used only for program-
ming.
Software support for the QL80FC device is available
through the Quick
Works
TM
development package.
This turnkey PC-based Quick
Works
package, shown
in Figure 6, provides a complete ESP software solu-
tion with design entry, logic synthesis, place and
route, and simulation. Quick
Works
includes VHDL,
Verilog, schematic, and mixed-mode entry with fast
and efficient logic synthesis provided by the inte-
grated Synplicity Synplify Lite
TM
tool, specially tuned
to take advantage of the QL80FC architecture.
Quick
Works
also provides functional and timing sim-
ulation for guaranteed timing and source-level debug-
ging.
The UNIX-based Quick
Tools
TM
package is a subset of
Quick
Works
and provides a solution for designers
who use schematic-only design flow or third-party
tools for design entry, synthesis, or simulation.
FIGURE 6. QuickWorks Tool Suite
Development Tools
MODE[1:0]
WA[a:0]
WD[w:0]
WE
WCLK
RAM Module
ASYNCRD
RA[a:0]
RD[w:0]
RE
RCLK
JTAG S
UPPORT
D
EVELOPMENT
T
OOLS
Schematic
Turbo
HDL Editor
Third Party
Design
Entry
& Synthesis
Third Party
Simulation
VHDL/
Verilog
SCS
Tools
Silos III
Simulator
SpDE
Mixed-Mode Design
Synplify-
SyHDL
Quick
Works
Design Software
Aldec
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL80FC-APQ208C | Telecomm/Datacomm |
| QL80FC-APQ208I | Telecomm/Datacomm |
| QL80FC | Programmable Fibre Channel ENDEC(可編程光纖信道編解碼器) |
| QL82SD | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PB516 | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL80FC-APQ208C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL80FC-APQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL8150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250-6PQN208C-5690 | 制造商:QuickLogic Corporation 功能描述: |
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