- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361294 > QL8025 (Electronic Theatre Controls, Inc.) LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | QL8025 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| 中文描述： | 低功耗FPGA配合力性能密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 3/49頁 |
| 文件大?。?/td> | 739K |
| 代理商： | QL8025 |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
Preliminary
6
!&
The Eclipse-II
logic cell structure is presented in
0
today's register-intensive designs.
. This architectural feature addresses
The Eclipse-II logic cell structure presented in
0
cell. It is designed for wide fan-in and multiple, simultaneous output funtions. Both registers share
CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its
input. The register can be loaded from the NZ output or directly from a dedicated input.
is a dual register, multiplexor-based logic
NOTE:
'&&&(&(&'&&'
&''')*+,-&&'.+/'
&&&&&&&'&&
The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven two-
to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell
has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17
simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic
capacity and fan-in of the logic cell accommodates many user functions with a single level of logic
delay while other architectures require two or more levels of delay.
01&,&
""
'"
&',
',
Multiplexer
16:1
5 ns
2.8 ns
Parity Tree
24
6 ns
3.4 ns
Counter
36
6 ns
3.4 ns
16 bit
250 MHz
450 MHz
32 bit
250 MHz
450 MHz
FIFO
128 x 32
155 MHz
280 MHz
256 x 16
155 MHz
280 MHz
128 x 64
155 MHz
280 MHz
Clock-to-Out
4.5 ns
2.5 ns
System clock
200 MHz
400 MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL8050 | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8150 | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250 | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8325 | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL80FC-APB456C | Telecomm/Datacomm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL8050 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL80FC-APB456C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL80FC-APB456I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL80FC-APQ208C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL80FC-APQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。