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參數(shù)資料
| 型號(hào)： | QL8025 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| 中文描述： | 低功耗FPGA配合力性能密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 12/49頁 |
| 文件大小： | 739K |
| 代理商： | QL8025 |
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Preliminary
0
or registered. This is identical to that of the flow for the output cell. For combinatorial control
operation data is routed from the logic array through a multiplexer to the three-state control. The
IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the same bank.
For registered control operation, the array logic drives the D input of the OE cell register which
in turn drives the three-state control through a multiplexer. The multiplexer allows either a
combinatorial or a registered signal to be driven to the three-state control.
When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell
register to be used for registered feedback into the logic array.
I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from
the regular routing resources, from one of the global networks, or from two IOCTRL input pins
per bank of I/O's. The CLK and RESET signals share common lines, while the clock enables for
each register can be independently controlled. I/O interface support is programmable on a per
bank basis. The two larger Eclipse-II devices contain eight I/O banks.The two smaller Eclipse-II
devices contain two I/O banks per device.
3
illustrates the I/O bank configurations.
Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and
INREF supply inputs. A mixture of different I/O standards can be used on the device; however,
there is a limitation as to which I/O standards can be supported within a given bank. Only
standards that share a common VCCIO and INREF can be shared within the same bank (e.g. PCI
and LVTTL).
+"
)*,
&
Each I/O has programmable slew rate capability—the slew rate can be either fast or slow. The
slower rate can be used to reduce the switching times of each I/O.
Embedded RAM Blocks
PLL
PLL
Fabric
Embeded Computational Units
Embedded RAM Blocks
PLL
PLL
VCCIO 0
INREF 0
VCCIO 1
INREF 1
VCCIO 2
INREF 2
VCCIO 3
INREF 3
INREF 4
VCCIO 4
INREF 5
VCCIO 5
INREF 6
VCCIO 6
INREF 7
VCCIO 7
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