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參數(shù)資料
| 型號(hào)： | Q67126-C2042 |
| 廠(chǎng)商： | SIEMENS AG |
| 元件分類(lèi)： | 8位微控制器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁(yè)數(shù)： | 41/65頁(yè) |
| 文件大?。?/td> | 427K |
| 代理商： | Q67126-C2042 |
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Semiconductor Group
41
1997-10-01
C540U
C541U
The following
table 9
contains the functional description of all C517A-2E pins which are required for
OTP memory programming.
Table 9
Pin Definitions and Functions in Programming Mode
Symbol
Pin Numbers
I/O*) Function
P-LCC-44 P-SDIP-52
RESET
10
12
I
Reset
This input must be at static “1“ (active) level during the
whole programming mode.
PMSEL0
PMSEL1
11
13
13
16
I
I
Programming mode selection pins
These pins are used to select the different access
modes in programming mode. PMSEL1,0 must satisfy
a setup time to the rising edge of PALE. When the
logic level of PMSEL1,0 is changed, PALE must be at
low level.
PMSEL
1
0
PSEL
14
17
I
Basic programming mode select
This input is used for the basic programming mode
selection and must be switched according
figure 10-
23
.
PRD
15
18
I
Programming mode read strobe
This input is used for read access control for OTP
memory read, version byte read, and lock bit read
operations.
PALE
16
19
I
Programming mode address latch enable
PALE is used to latch the high address lines. The high
address lines must satisfy a setup and hold time to/
from the falling edge of PALE. PALE must be at low
level whenever the logic level of PMSEL1,0 is
changed.
XTAL2
20
23
O
XTAL2
Output of the inverting oscillator amplifier.
*) I = Input
O = Output
PMSEL
Access Mode
0
0
Reserved
0
1
Read version bytes
1
0
Program/read lock bits
1
1
Program/read OTP memory byte
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