參數(shù)資料
型號: PSMN005-25D
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: N-channel logic level TrenchMOS transistor
中文描述: 75 A, 25 V, 0.0075 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝: PLASTIC, DPAK-3
文件頁數(shù): 6/9頁
文件大?。?/td> 99K
代理商: PSMN005-25D
Philips Semiconductors
Product specification
N-channel logic level TrenchMOS
transistor
PSMN005-25D
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
) versus avalanche time (t
AV
);
unclamped inductive load
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
10
20
30
40
Gate charge, QG (nC)
50
60
70
80
90
100
110
Gate-source voltage, VGS (V)
ID = 75 A
VDD = 15 V
Tj = 25 C
1
0.001
10
100
0.01
0.1
1
10
Avalanche time, t
AV
(ms)
Maximum Avalanche Current, I
AS
(A)
Tj prior to avalanche = 150 C
25 C
0
5
10
15
20
25
30
35
40
45
50
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
175 C
VGS = 0 V
October 1999
6
Rev 1.100
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