參數(shù)資料
型號: PSD954F2
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
中文描述: 在8片位微控制器可配置存儲系統(tǒng)(用于8位微控制器的可配置存儲器系統(tǒng))
文件頁數(shù): 19/90頁
文件大小: 543K
代理商: PSD954F2
Preliminary Information
PSD9XX Family
15
9.0
The
PSD9XX
Functional
Blocks
As shown in Figure 1, the PSD9XX consists of six major types of functional blocks:
J
Memory Blocks
J
PLD Blocks
J
Bus Interface
J
I/O Ports
J
Power Management Unit
J
JTAG Interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
9.1 Memory Blocks
The PSD9XX has the following memory blocks:
The main Flash memory
Secondary Flash memory
SRAM.
The memory select signals for these blocks originate from the Decode PLD (DPLD) and
are user-defined in PSDsoft.
Table 8 summarizes which versions of the PSD9XX contain which memory blocks.
Main Flash
Secondary Flash Block
Block Size
Device
Flash Size
Sector Size
Sector Size
SRAM
PSD913F2
128KB
16KB
32KB
8KB
2KB
PSD934F2
256KB
32KB
32KB
8KB
8KB
Table 8. Memory Blocks
9.1.1 Main Flash and Secondary Flash Memory Description
The main Flash memory block is divided evenly into eight sectors. The secondary Flash
memory is divided into four sectors of eight Kbytes each. Each sector of either memory
can be separately protected from program and erase operations.
Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte.
Flash sector erasure may be suspended while data is read from other sectors of memory
and then resumed after reading.
During a program or erase of Flash, the status can be output on the Rdy/Bsy pin of Port
C3. This pin is set up using PSDsoft.
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