參數(shù)資料
型號： PSD854F2A-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
封裝： ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 113/128頁
文件大?。?/td> 1045K
代理商： PSD854F2A-90UT
PSD8XXFX
Reset timing and device status at reset
Doc ID 7833 Rev 7
18
Reset timing and device status at reset
18.1
Power-up reset
Upon Power-up, the PSD requires a Reset (RESET) pulse of duration tNLNH-PO after VCC is
steady. During this period, the device loads internal configurations, clears some of the
registers and sets the Flash memory into operating mode. After the rising edge of Reset
(RESET), the PSD remains in the Reset mode for an additional period, tOPR, before the first
memory access is allowed.
The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be low, Write Strobe (WR, CNTL0) high, during Power On
Reset for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of Write Strobe (WR, CNTL0). Any Flash memory WRITE
cycle initiation is prevented automatically when VCC is below VLKO.
18.2
Warm reset
Once the device is up and running, the device can be reset with a pulse of a much shorter
duration, tNLNH.
The same tOPR period is needed before the device is operational after warm reset.
Figure 33 shows the timing of the Power-up and warm reset.
18.3
I/O pin, register and PLD status at Reset
Table 34 shows the I/O pin, register and PLD status during Power On Reset, warm reset and
Power-down mode. PLD outputs are always valid during warm reset, and they are valid in
Power On Reset once the internal PSD Configuration bits are loaded. This loading of PSD is
completed typically long before the VCC ramps up to operating level. Once the PLD is active,
the state of the outputs are determined by the PSDabel equations.
18.4
Reset of Flash memory erase and program cycles (on the
PSD834Fx)
A Reset (RESET) also resets the internal Flash memory state machine. During a Flash
memory program or erase cycle, Reset (RESET) terminates the cycle and returns the Flash
memory to the Read mode within a period of tNLNH-A.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD854F2V-12JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-12MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC
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